ATmega32U2 datasheet(45/314 Pages) ATMEL

45 / 314 page

7799B–AVR–07/09

ATmega8U2/16U2/32U2

enabled and the input signal is left floating or have an analog signal level close to V

CC/2, the

input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V

CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1). Refer to

“DIDR1 – Digital Input Disable Register 1” on page 225 for details.

9.9.6

On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode,

the main clock source is enabled, and hence, always consumes power. In the deeper sleep

modes, this will contribute significantly to the total current consumption.

9.10

9.10.1

SMCR – Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

• Bit 7:4 - Reserved bits

These bits are reserved and will always read as zero.

• Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 9-2.

Note:

1. Standby modes are only recommended for use with external crystals or resonators.

• Bit 0– SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

Bit

76543210

0x33 (0x53)

––––

SM2

SM1

SM0

SMCR

Read/Write

RRRR

R/W

Initial Value

00000000

Table 9-2.

Sleep Mode Select

SM2

SM1

SM0

Sleep Mode

000

Idle

001

Reserved

010

Power-down

011

Power-save

100

Reserved

101

Reserved

Standby(1)

Extended Standby(1)

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