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ATmega32U2 Datasheet(PDF) 40 Page - ATMEL Corporation |
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ATmega32U2 Datasheet(HTML) 40 Page - ATMEL Corporation |
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40 / 314 page  40 7799B–AVR–07/09 ATmega8U2/16U2/32U2 8.11.6 PLLCSR – PLL Control and Status Register • Bit 7:5 – Res: Reserved Bits These bits are reserved bits in the ATmega8U2/16U2/32U2 and always read as zero. • Bit 4 – DIV5 PLL Input Prescaler (1:5) • Bit 3 – DIV3 PLL Input Prescaler (1:3) • Bit 2 – PINDIV PLL Input Prescaler (1:1, 1:2) These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the PLL from either a 8 or 16 MHz input. When using a 8 MHz clock source, this bit must be set to 0 before enabling PLL (1:1). When using a 16 MHz clock source, this bit must be set to 1 before enabling PLL (1:2). • Bit 3:2 – Res: Reserved Bits These bits are reserved and always read as zero. Table 8-9. Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 00 00 1 00 01 2 00 10 4 00 11 8 01 00 16 01 01 32 01 10 64 0 1 1 1 128 1 0 0 0 256 10 01 Reserved 10 10 Reserved 10 11 Reserved 11 00 Reserved 11 01 Reserved 11 10 Reserved 11 11 Reserved Bit 7 65 43 210 0x29 (0x49) – – – DIV5 DIV3 PINDIV PLLE PLOCK PLLCSR Read/Write RR R R/W RR R/W R Initial Value 0 0 0 0 0 0 0 0 |
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