ATmega32U2 datasheet(52/314 Pages) ATMEL

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7799B–AVR–07/09

ATmega8U2/16U2/32U2

when the counter reaches a given time-out value. The WDT gives an interrupt or a system reset

when the counter reaches two times the given time-out value. In normal operation mode, it is

required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the coun-

ter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or

system reset will be issued.

Figure 10-8. Watchdog Timer

In Interrupt mode, the WDT gives an interrupt when the timer expires two times. This interrupt

can be used to wake the device from sleep-modes, and also as a general system timer. One

example is to limit the maximum time allowed for certain operations, giving an interrupt when the

operation has run longer than expected.

In System Reset mode, the WDT gives a reset when the timer expires two times. This is typically

used to prevent system hang-up in case of runaway code.

The third mode, Interrupt and System Reset mode, combines the other two modes by first giving

an interrupt and then switch to System Reset mode. This mode will for instance allow a safe

shutdown by saving critical parameters before a system reset.

In addition to these modes, the early warning interrupt can be enabled in order to generate an

interrupt when the WDT counter expires the first time.

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-

tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt

mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, altera-

tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE or

changing time-out configuration is as follows:

In the same operation, write a logic one to the Watchdog change enable bits WDCE

and WDE. A logic one must be written to WDE regardless of the previous value of the

WDE bit and even if it will be cleared after the operation.

Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as

desired, but with the WDCE bit cleared. This must be done in one operation.

128kHz

OSCILLATOR

WDP0

WDP1

WDP2

WDP3

WATCHDOG

RESET

WDE

WDIF

WDIE

WDEWIE

MCU RESET

INTERRUPT

EARLY WARNING

INTERRUPT

CLOCK

DIVIDER

OSC/1

OSC/3

OSC/5

OSC/7

ATmega32U2 Datasheet(PDF) 52 Page - ATMEL Corporation

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