ATmega32U2 datasheet(18/314 Pages) ATMEL

18 / 314 page

7799B–AVR–07/09

ATmega8U2/16U2/32U2

The 32 general purpose working registers, 64 I/O registers, and the 512/512/1024bytes of inter-

nal data SRAM in the ATmega8U2/16U2/32U2 are all accessible through all these addressing

modes. The Register File is described in “General Purpose Register File” on page 10.

Figure 7-2.

Data Memory Map

7.2.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU cycles as described in Figure 7-3.

Figure 7-3.

On-chip Data SRAM Access Cycles

7.3

EEPROM Data Memory

The ATmega8U2/16U2/32U2 contains 512/512/1024 bytes of data EEPROM memory. It is orga-

nized as a separate data space, in which single bytes can be read and written. The EEPROM

has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and

the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register.

32 R

egisters

64 I/O

egisters

nternal S RAM

(256/512/1024

x 8)

$0000 - $001F

$0020 - $005F

$2FF/$2FF/$4FF (8U2/16U2/32U2)

$0060 - $00FF

ata Memory

160 E

xt I/O

eg.

$0100

clk

Data

Address

Address valid

Compute Address

CPU

Memory Access Instruction

Next Instruction

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