ATmega32U2 datasheet(143/314 Pages) ATMEL

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7799B–AVR–07/09

ATmega8U2/16U2/32U2

means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin

is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous

with the master clock generator. When the SS pin is driven high, the SPI slave will immediately

reset the send and receive logic, and drop any partially received data in the Shift Register.

17.3.2

Master Mode

When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the

direction of the SS pin.

If SS is configured as an output, the pin is a general output pin which does not affect the SPI

system. Typically, the pin will be driving the SS pin of the SPI Slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin

is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin

defined as an input, the SPI system interprets this as another master selecting the SPI as a

slave and starting to send data to it. To avoid bus contention, the SPI system takes the following

actions:

The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of

the SPI becoming a Slave, the MOSI and SCK pins become inputs.

The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG

is set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-

bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the

MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master

mode.

17.4

Data Modes

There are four combinations of SCK phase and polarity with respect to serial data, which are

determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure

17-3 and Figure 17-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-

nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing

Table 17-3 and Table 17-4, as done below:

ATmega32U2 Datasheet(PDF) 143 Page - ATMEL Corporation