ATmega32U2 datasheet(166/314 Pages) ATMEL

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166

7799B–AVR–07/09

ATmega8U2/16U2/32U2

stop sending characters. RTS usage and so associated flow control is enabled using RTSEN bit

in UCSRnD.

Figure 18-8. shows a reception example.

Figure 18-8. Reception Flow Control Waveform Example

Figure 18-9. RTS behavior

RTS will rise at 2/3 of the last received stop bit if the receive fifo is full.

To ensure reliable transmissions, even after a RTS rise, an extra-data can still be received and

stored in the Receive Shift Register.

18.10.2

Transmission Flow Control

The transmission flow can be controlled by hardware using the CTS pin controlled by the exter-

nal receiver. The aim of the flow control is to stop transmission when the receiver is full of data

(CTS = 1). CTS usage and so associated flow control is enabled using CTSEN bit in UCSRnD.

The CTS pin is sampled at each CPU write and at the middle of the last stop bit that is

curently being sent.

Figure 18-10. CTS behavior

RTS

RXD

C1 C2

FIFO

CPU Read

Index

RTS

RXD

Start

Byte0

Stop

Start

Byte1

Stop

Read from CPU

Start

Byte2

1 additional byte may be sent

if the transmitter misses the RTS trig

CTS

TXD

Start

Byte0

Stop

Start

Byte1

Stop

Start

Byte2

sample

Write from CPU

sample

ATmega32U2 Datasheet(PDF) 166 Page - ATMEL Corporation

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