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ATmega32U2 Datasheet(PDF) 225 Page - ATMEL Corporation |
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ATmega32U2 Datasheet(HTML) 225 Page - ATMEL Corporation |
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225 / 314 page  225 7799B–AVR–07/09 ATmega8U2/16U2/32U2 When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. 22.2.2 ACMUX – Analog Comparator Input Multiplexer • Bit 2, 0 – CMUX2:0: Analog Comparator Selection Bits The value of these bits selects which combination of analog inputs are connected to the analog comparator. The different settings are shown in Table 22-2. 22.2.3 DIDR1 – Digital Input Disable Register 1 • Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AINx pin is disabled. The corre- sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. Table 22-1. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 01 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge. Bit 76543210 (0x7D) – – – – – CMUX2 CMUX1 CMUX0 ACMUX Read/Write RRRRR R/W R/W R/W Initial Value 00000000 Table 22-2. CMUX2:0 Settings CMUX2 CMUX1 CMUX0 Comparator Input 000 AIN1 001 AIN2 010 AIN3 011 AIN4 100 AIN5 101 AIN6 110 Reserved 111 Reserved Bit 76543210 – AIN6D AIN5D AIN4D AIN3D AIN2D AIN1D AIN0D DIDR1 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000 |
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