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ATmega32U2 Datasheet(PDF) 269 Page - ATMEL Corporation |
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ATmega32U2 Datasheet(HTML) 269 Page - ATMEL Corporation |
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269 / 314 page  269 7799B–AVR–07/09 ATmega8U2/16U2/32U2 26.6 External Interrupts Characteristics 26.7 SPI Timing Characteristics See Figure 26-3 and Figure 26-7 for details. Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12 MHz - 3 t CLCL for fCK > 12 MHz Table 26-5. Asynchronous External Interrupt Characteristics Symbol Parameter Condition Min Typ Max Units tINT Minimum pulse width for asynchronous external interrupt 50 ns Table 26-6. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 17-5 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master TBD 4 Setup Master 10 5Hold Master 10 6 Out to SCK Master 0.5 • tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9SS low to out Slave 15 10 SCK period Slave 4 • tck 11 SCK high/low(1) Slave 2 • tck 12 Rise/Fall time Slave TBD 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 20 |
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