33905 datasheet(30/91 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33904/5

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

Figure 17. Analog Multiplexer Block Diagram

DGB (DGB) AND DEBUG MODE

The DBG pin has 2 functions:

Primary function:

It is an output used to set the device in Debug Mode. This

is achieved by applying a voltage between 8V and 10V, at the

debug terminal, and then powering up the device (ref to state

diagram). When device leaves the INIT reset mode and enter

in INIT mode, device detects that voltage at debug terminal is

within the 8-10V range, and activate the debug mode.

When debug mode is detected, no watchdog SPI refresh

commands is necessary. This allow easy debug of the

hardware and software routines (i.e SPI commands).

Device is in debug mode is reported by SPI flag. While in

de bug mode, when voltage at DBG terminal falls below the

8-10V range, the debug mode is left, and device start W/D

operation, and expect proper W/D refresh.Debug mode can

be left by SPI. Such command is recommended to avoid

staying in debug mode in case of unwanted debug mode

selection (pin FMEA). SPI command to leave debug has

higher priority than providing 8-10V at debug pin.

Secondary function:

The resistor connected between DBG pin and gnd selects

the Fail Safe Mode operation. DBG pin can also be

connected directly to gnd (this prevent usage of debug

mode).

Flexibility is provided to the user to select SAFE output

operation via a resistor at the DBG pin or via SPI command.

The SPI command has higher priority than the hardware

selection via Debug resistor.

When the Debug mode is selected, the SAFE modes can

not be configured via the resistor connected at DBG pin.

SAFE

Safe output terminal

This pin is an output which is asserted low in case a fault

event occurs. The objective is to drive electrical safe circuitry

and set the ECU in a know sate independent of the MCU and

SBC, once a failure has been detected.

The SAFE output structure is an open drain, without a pull-

up. No current flow is allowed when SAFE is forced externally

to a high-voltage (< 40V).

INTERRUPT (INT)

The INT output is asserted low or generate a low pulse

when an interrupt condition occurs. The INT condition is

enabled in the INT register. The selection of low level or pulse

as well as pulse duration are selected by SPI.

No current will flow inside the INT structure when VDD is

low, in Low Power VDD OFF Mode. This allows the

connection of an external pull resistor, and connection of an

INT pin from other ICs without extra consumption in

unpowered mode.

VBAT

VSUP_1

S_in

I/O-1

I/O-0

Multiplexer

VDD-I_COPY

RM(*)

(*)Optional

A/D in

MCU

S_iddc

MUX-OUT

S_g3.3

Temp

VSENSE

S_g5

RSENSE 1k

RMI

S_ir

S_in

Vref: 2.5V

5V-CAN

S-i/o_att

All swicthes and resistor are configured and controlled via the

SPI.

RM: internal resistor connected when VREG current monitor is

used.

S_g3.3 and S_g5 for 5.0V or 3.3V MCU.

S_iddc to select VDD regulator current copy.

S_in1 for Low Power Mode resistor bridge disconnection.

S_ir to switch on/off of the internal RMI resistor.

buffer

33905 Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

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