33905 datasheet(43/91 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33904/5

FAIL SAFE OPERATION

BEHAVIOR AT POWER UP AND POWER DOWN

Figure 24. Safe Operation Flow Chart

Conditions to set SAFE pin active low:

Watchdog refresh issue: SAFE activated at 1st reset pulse

or at the second consecutive reset pulse (selected by bit 4,

INIT W/D register).

Vdd low: Vdd < RST-TH. SAFE pin is set low at same time

as Reset pin is set low.

The RESET pin is monitored to verify that reset is not

clamped to a low level preventing the MCU to operate. If this

is the case, the Safe Mode is entered.

W/D failure

Vdd low:

Rst s/c gnd:

- SAFE low

8 consecutive W/D failure (5)

State A: Rdbg<6k AND

- SAFE low

- Reset: 1ms

- Vdd ON

- Reset low

INIT,

b) ECU external signal

State B1: Rdbg=15k AND

State B3:

State B2:

- SAFE low

- Reset low

- Vdd OFF

a) Evaluation of

Bus idle time out expired

Normal, FLASH

VDD<VDD_UVTH

Rst <2.5V, t>100ms

Device state:

RESET

bit 4, INIT W/D = 1 (1)

detection of 2nd

consecutive W/D failure

SAFE low

SAFE high

SAFE low

Reset: 1ms pulse

bit 4, INIT W/D = 0 (1)

Reset: 1ms pulse

Normal Request

power up, or SPI

at DBG pin during

RESET

SAFE pin release

failure recovery, SAFE pin remains low

SPI (3)

AND Bus idle time out expired

RESET

Wake up (2), Vdd ON, SAFE pin remains low

(SAFE high)

Failure events

1) bit 4 of INIT Watchdog register

2) Wake up event: CAN, LIN or I/O-1 high level (if I/O-1 wake up previously enabled)

3) SPI commands: 0xDD00 or 0xDD80 to release SAFE pin

4) Recovery: reset low condition released, Vdd low condition released, correct SPI W/D refresh

5) detection of 8 consecutive W/D failures: no correct SPI W/D refresh command occurred for duration of 8 x 256ms.

6) Dynamic behavior: 1ms reset pulse every 256ms, due to no W/D refresh SPI command, and device state transition

Legend:

Rdbg=33k AND I/O-1 low

Rdbg=47k AND I/O-1 low

- Vdd ON

(6)

- SAFE low

- Vdd ON

- Reset low

periodic pulse

State A: Rdbg<6k AND

W/D failure

(Vdd low or Rst s/c gnd) failure

Resistor detected

between RESET and NORMAL REQUEST mode, or INIT RESET and INIT modes.

- bus idle time out

- I/O-1 monitoring

monitoring (7):

7) 8 second timer for bus idle time out. I/O-1 high to low transition.

SAFE operation flow chart

33905 Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc

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