33905 datasheet(72/91 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33904/5

SERIAL PERIPHERAL INTERFACE

DETAIL OF CONTROL BITS AND REGISTER MAPPING

Table 33. INT Register, INT

MOSI First byte [15-8]

[b_15 b_14] 10_010 [P/N]

MOSI Second Byte, bits 7-0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

01 10_ 010P

CAN failure

MCU req

LIN1 fail

LIN0fail

I/O

SAFE

Vmon

Default state

Condition for default

POR

Bits

Description

CAN failure - control bit for CAN failure INT (CANH/L to GND, VDD or VSUP, CAN over-current, Driver Over Temp, TX-PD,

RX-PR, RX2HIGH, and CANBUS Dominate clamp)

INT disable

INT enable.

MCU req - Control bit to request an INT. INT will occur once when the bit is enable

INT disable

INT enable.

not implemented in MC33904

INT disable

INT enable.

not implemented in MC33904

INT disable

INT enable.

I/O - Bit to control I/O interruption: I/O Wake-up

INT disable

INT enable.

SAFE - description to be done

INT disable

INT enable.

Vmon - enable interruption by voltage monitoring of one of the voltage regulator: VAUX, 5V-CAN, VDD (IDD Over-current,

VDD_Temp_prewarning), VSUV, VSOV, VSENSElow, 5V-CAN low or thermal shutdown, VAUX low or VAUX over-current

INT disable

INT enable.

33905 Datasheet(PDF) 72 Page - Freescale Semiconductor, Inc

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