33905 datasheet(45/91 Pages) FREESCALE

45 / 91 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33904/5

FAIL SAFE OPERATION

BEHAVIOR AT POWER UP AND POWER DOWN

SAFE mode B1, B2 and B3 illustration:

The figure below illustrates the event, and consequences when SAFE Mode B1, B2 or B3 is selected via the appropriate debug

resistor or SPI configuration.

Figure 26. SAFE Modes B1, B2 or B3 Behavior Illustration

DBG resistor => safe state B1

Vdd

RSTb

SAFE

CAN bus

CAN bus idle time

I/O-1

I/O-1 high to low transition

DBG resistor => safe state B2

DBG resistor => safe state B3

CAN bus

CAN bus idle time

I/O-1

I/O-1 high to low transition

step 2:

RSTb

Vdd

failure event, i.e W/D

SAFE

OFF state ON state

8 x 256ms delay time to enter in SAFE mode

to evaluate resistor at DBG pin

and monitor ECU external events

1st

8th

2nd

step 1: Failure illustration

RSTb

Vdd

failure event, Vdd low

SAFE

OFF state ON state

100ms delay time to enter in SAFE mode

to evaluate resistor at DBG pin

and monitor ECU external events

Vdd_UV th

100ms

gnd

RSTb

Vdd

failure event, Reset s/c gnd

SAFE

OFF state

ON state

100ms deglitcher time to activate SAFE and

enter in SAFE mode to evaluate resistor at DBG pin

and monitor ECU external events

2.5V

100ms

Vdd

RSTb

SAFE

Vdd OFF

RSTb

SAFE

Vdd

If Vdd failure recovered

Vdd < Vdd_UVth

Vdd OFF

gnd

step 3: Consequences for Vdd

If Reset s/c gnd recovered

Behavior illustration for safe state B (Rdg > 10kOhms)

ECU external event to

Rdbg resistor or

disable Vdd based on

SPI configuration

Exclusive detection of

33905 Datasheet(PDF) 45 Page - Freescale Semiconductor, Inc

33905 Datasheet(HTML) 45 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datasheet Download

Link URL