PixArt Imaging Inc.

PAC107

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

8

PixArt Imaging Inc.

V1.4, Aug, 2005

Reg_21[4]

Toyt

R/W

0

-

Toy timing enable

Reg_21[3]

aegenh

R/W

1

-

AE/AG enable

Reg_21[2:1]

Edge-gn[1:0]

R/W

00

-

Edge gain

Reg_21[0]

Vlrst_outh

R/W

0

0

External vlrst enable

Reg_22[7]

Shr_we2

R/W

1

0

CDS extension

Reg_22[6]

Intvddy

R/W

1

-

Internal array vdd

Reg_22[5]

Intvref

R/W

1

-

Internal voltage reference

Reg_22[4]

Cdsenh

R/W

1

-

CDS enable

Reg_22[3]

Dacenh

R/W

1

0

DAC enable

Reg_22[2]

Pgaenh

R/W

1

-

PGA enable

Reg_22[1]

Adcenh

R/W

1

-

ADC enable

Reg_22[0]

Dqioenl

R/W

0

-

DQIO enable / tri-stage

Reg_23[7]

vlrst_enh

R/W

0

0

vlrst enable

Reg_23[6]

Vr

R/W

0

1

Vref option

Reg_23[5]

Vy

R/W

0

1

Array vdd option

Reg_23[4:3]

Regfast[1:0]

R/W

00

-

Fast mode for Regulator

Reg_23[2]

Cdsfast

R/W

0

-

Fast mode for CDS

Reg_23[1]

Pgafast

R/W

0

-

Fast mode for PGA

Reg_23[0]

Adcfast

R/W

0

-

Fast mode for ADC

Reg_24[7:3]

RSV

R/W

-

-

Reserved

Reg_24[2]

Dacscan

R/W

0

-

DAC test mode

Reg_24[1]

Pgascan

R/W

0

-

PGA test mode

Reg_24[0]

Frstenl

R/W

1

-

Frame reset enable

Reg_25[7:1]

RSV

-

-

-

Reserved

Reg_25[0]

fast_i2c

R/W

0

-

Fast update for Reg_13 ~

Reg_18

Reg_26[7:5]

RSV

R/W-

-

-

Reserved

Reg_26[4:0]

Pga_report[4:0]

R

-

-

PGA code report (AE enable)

Reg_27[7:0]

Ne_report[7:0]

R

-

-

NE report (AE enable)

Reg_28[7]

RSV

-

-

-

Reserved

Reg)28[6:0]

Ny_report[6:0]

R

-

-

NY report (AE enable)