PixArt Imaging Inc.

PAC107

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

29

PixArt Imaging Inc.

V1.4, Aug, 2005

4.2 TIMER/COUNTERS

Timer 0

Timer 0 can be a timer or event counter in four modes of operation. It’s controlled by the

high-nibble of the TMOD register and bits 5, 4, 1, and 0 of the TCON register. The TMOD

mode of operation (M1, M0). The TCON register provides timer 0 control functions:

overflag (TF0), run control (TR0), interrupt flag (IE0), and interrupt type control (IT0). For

normal timer operation (GATE = 0), setting TR0 allows TL0 to be incremented by the

selected input. Setting GATE and TR0 allows

0

INT

to control timer operation.

Timer0/Mode 0 (13-bit Timer)

Mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (TH0 register)

with a modulo 32 pre-scalar implemented with the lower five bits of the TL0 register. The

upper three bits of TL0 register are indeterminate and should be ignored. Pre-scalar

overflow increments the TH0 register.

Timer 0/ Mode 1 (16-bit Timer)

Mode 1 configures timer 0 as a 16-bit timer with TH0 and TL0 connected in cascade.

The selected input increments TL0.

Timer 0/ Mode 2 (8-bit Timer With Auto-reload)

12

0

1

XTAL1

Tx

THx

(8 Bits)

TLx

(8 Bits)

Overflow

Interrupt

Request

TFx

GATEx

TRx

x = 0 or 1

Mode 0: 13-bit Time/Counter

Mode 1: 16-bit Time/Counter

C/ Tx

INTx

Timer 0/1 in Mode 0 and Mode 1