PixArt Imaging Inc.

PAC107

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

2

PixArt Imaging Inc.

V1.4, Aug, 2005

1. Pin Description

1.1 80-pin LCC

Pin No.

Name

Type

Definition

1

VRT

Bypass

Top-voltage reference for analog circuit

2

GNDA

G

Analog ground

3

/EA

I

Enable bar of external ROM, “1” for internal ROM

4

ROM_AR13

O

Address for external ROM, bit 13

5

ROM_AR12

O

Address for external ROM, bit 12

6

ROM_AR11

O

Address for external ROM, bit 11

7

PWM1

O

8032, Programmable Pulse-width-modulation output

8

ROM_AR10

O

Address for external ROM, bit 10

9

ROM_AR9

O

Address for external ROM, bit 9

10

ALE

O

Address latch pulse for SRAM-address

11

RST

I

Chip reset

12

ROM_AR8

O

Address for external ROM, bit 8

13

ROM_AR7

O

Address for external ROM, bit 7

14

ROM_AR6

O

Address for external ROM, bit 6

15

ROM_AR5

O

Address for external ROM, bit 5

16

VDDD

P

Digital power

17

ROM_AR4

O

Address for external ROM, bit 4

18

ROM_AR3

O

Address for external ROM, bit 3

19

ROM_AR2

O

Address for external ROM, bit 2

20

ROM_AR1

O

Address for external ROM, bit 1

21

ROM_AR0

O

Address for external ROM, bit 0

22

ROM_D0

I

Data from external ROM, bit 0

23

ROM_D1

I

Data from external ROM, bit 1

24

GNDD

G

Digital ground

25

ROM_D2

I

Data from external ROM, bit 2

26

ROM_D3

I

Data from external ROM, bit 3

27

ROM_D4

I

Data from external ROM, bit 4

28

ROM_D5

I

Data from external ROM, bit 5

29

ROM_D6

I

Data from external ROM, bit 6

30

P3_6(/WR)

O

8032, P3_6 (/WR) – Write pulse of SRAM

31

P3_7(/RD)

O

8032, P3_7 (/RD) – Read pulse of SRAM

32

NC

NC

Not connected

33

ROM_D7

I

Data from external ROM, bit 7

34

P2_0

IO

8032, P2_0

35

P2_1

IO

8032, P2_1

36

PWM2

O

8032, Programmable Pulse-width-modulation output

37

P2_2

IO

8032, P2_2

38

P2_3

IO

8032, P2_3

39

VDDD

P

Digital power