PixArt Imaging Inc.

PAC107

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35

PixArt Imaging Inc.

V1.4, Aug, 2005

The input clock advances TL0 at frequency of Fosc/2. The timer repeatedly counts to

overflow from a preloaded value. At overflow, the contents of the RCAP2H and RCAP2L

registers are loaded into TH2/TL2. In this mode, timer 2 overflows do not generates

interrupts. The formula gives the clock-out frequency as a function of the system oscillator

frequency and the value in the RCAP2H and RCAP2L registers:

Watchdog Timer

The watchdog timer has system reset functions. By setting WD1-1, WD1-0 (CKCON, 8Eh)

to choose

17

2,

20

2,

23

2or

26

2

counter for Watchdog Timer. As the Watchdog Timer

overflow, sets WDTRSTFg (in register WDCON, D8h) and finally resets the MCU. If

MCU is reset by watchdog Timer , WDTRSTFg remains one and POR (in register

WDCON, D8h) is zero. On the other hand, if RISC 52 has been power-on reset,

WDTRSTFg is zero and POR one.

Fosc

Mode

Auto-reload Mode

Capture Mode

Baud Rate Generator Mode

Programmable Clock-Out

RCLK OR TCLK

(in T2COON)

CP/RL2#

(in T2MOD)

T2OE

(in T2MOD)

0

0

1

X

0

1

X

0

0

0

X

1

Timer 2 Modes of Operation

T2OE

XTAL1

TR2

T2

0

1

TL2

(8 Bits)

Overflow

TH2

(8 Bits)

RCAP2H

RCAP2L

2

2

Interrupt

Request

EXF2

EXEN2

T2EX

C/ T2

Timer 2: Clock Out Mode