PixArt Imaging Inc.

PAC107

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PixArt Imaging Inc.

V1.4, Aug, 2005

3.1. MEMORY ORGANIZATION

In the RISC 52 the memory is organized as three address spaces and the program counter.

The memory spaces shown in memory map.

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16-bit Program Counter

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16kB Program Memory address space

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64kB External Data Memory address space

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256-byte Internal Data Memory address

The 14-bit Program Counter register provides the RISC 52 with its 16kB addressing

capabilities. The program Counter allows the user to execute calls and branches to any

location within the Program Memory space. There are no instructions that permit program

execution to move from the Program Memory space to any of the data memory spaces.

The 64k-byte External Data Memory address space is automatically accessed when the

MOVX instruction is executed. Note that user can extend the addressable data RAM space

by MUX the general I/O pins in port 1 and 3.

The Internal SRAM address space is 0 to 255 CPU internal usage. Four 8-Register Banks

occupy locations 0 through 31. The stack can be located anywhere in the Internal Data

RAM address space. In addition, 128 bit locations of the on-chip RAM are accessible

through Direct Addressing.