PixArt Imaging Inc.

PAC107

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13

PixArt Imaging Inc.

V1.4, Aug, 2005

Timer 2 Control Register.

TF2:

Timer2 Overflow flag. Cleared by software. TF2 can not be set when RCLK=1or

TCLK=1.

EXF2:

Timer 2 external flag. Set when either a capture or reload is caused by a negative

transition on T2EX, EXEN2=1. When Timer2 interrupt is enabled, EXF2=1 will

cause the CPU to vector of Timer2 ISR. EXF2 must be cleared by software.

RCLK: Receive Clock flag. Selects timer 2 overflow pulses (RCLK=1) or timer

1overfiow pulses (RCLK=0) as the baud rate generator for UART modes 1 & 3.

TCLK: Transmit Clock flag. Select Timer2 overflow pulses (TCLK=1) or timer 1

overflow pulses (TCLK=0) as the baud rate generator for serial port modes 1 & 3.

EXEN2:Timer 2 External Enable flag. EXEN2=1: Capture or reload when a negative

transition on T2EX unless timer 2 is being used as the baud rate generator for the

serial port. Clearing EXEN2 causes timer 2 to ignore events at T2EX.

TR2:

Timer 2 Run Control flag. Setting this bit starts the timer.

T

: Timer 2 Counter/Timer Select

T

= 0 Timer 2 counts the divided-down system clock.

T

= 1 Timer 2 counts when external pin T2 goes low.

CP/

2

RL

: Capture/Reload Bit

CP/

2

RL

=1: (if EXEN2=1), captures occurred at negative edge of T2EX.

CP/

2

RL

=0: (if EXEN2=1), auto-reloads occurred at negative edge of T2EX or

when Timer 2 overflowed.

(if RCLK =1 or TCLK = 1).CP/

2

RL

is ignored and timer 2 is auto-reloaded

when timer 2 overflow,

Timer 2 Mode Control Register.

Bit7-Bit2: Reserved

T2OE:

Timer 2 Output Enable flag. In the timer 2 clock-out mode, connects the

programmable clock output to external pin T2.

DCEN:

Down Count Enable flag. Configures timer 2 as an up/down counter.

T2MOD

Address:C9h

bit 7

bit 0

T2OE

DCEN