PixArt Imaging Inc.

PAC107

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16

PixArt Imaging Inc.

V1.4, Aug, 2005

IE1: Interrupt 1 Edge Detect. Set by hardware when interrupted at pin-

1

INT

. Cleared when

ISR is processed for edge-triggered.

IT1: Interrupt 1 Trigger Type Selection Bit.

IT1=1: Edge-triggered (hi-to-lo). IT1=0: Level-triggered (active low).

IE0: Interrupt 0 Edge Detect. Set by hardware when interrupted at pin-

0

INT

. Cleared when

ISR is processed for edge-triggered.

IT0: Interrupt 0 Trigger Type Selection Bit.

IT0=1: Edge-triggered (hi-to-lo). IT0=0: Level-triggered (active low).

Timer/Counter Mode Control Register.

GATE (TMOD.7 or TMOD.3): Timer1/Timer0 toggling gate control

When TRx(in TCON) is set and GATE=1, TIMER/COUNTERx will run only while

INTx pin is high(hardware control). When GATE=0, Timer/Counterx will run only

while TRx=1(software control).

M1 (TMOD.5), M0 (TMOD.4) :Mode select of Timer 1

M1 M0 MODE

Operation

0

0

0

1 bit Timer. 8-bit Timer/Counter (THx) with 5-bit pre-scalar (TLx)

0

1

1

16-bit Timer/Counter

1

0

2

8-bit auto-reload Timer/Counter. Reload from THx when overflow.

1

1

3

(Timer 0) TL0 is an 8-bit Timer and is controlled by Timer 1 control bits.

1

1

3

(Timer 1) Timer/Counter 1 is stopped.

TMOD

Address:89h

bit 7

bit 0

GATE

M1

M0

GATE

M1

M0

TIMER1

TIMER0

C/T

C/T