PixArt Imaging Inc.

PAC107

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27

PixArt Imaging Inc.

V1.4, Aug, 2005

programmed to be level-triggered or edge triggered. IT1 = 0,

1

INT

is triggered by

detected low at the pin. If IT1 = 1,

1

INT

is negative-edge triggered. External interrupts are

enabled with bits EX1in the IE register. Evens on the external interrupt pins set the

interrupt flags IE1 in TCON. These request bits are cleared by hardware vectors to service

routines only if the interrupt is negative-edge triggered. If the interrupt is level-triggered,

the interrupt service routine must clear the request bit. External hardware must release

1

INT

before the service routine completes, or an additional interrupt is requested.

External interrupt pins are sampled once when rising edge of oscillator clock. The interrupt

pin should hold for at least 3 clocks for level-detection. And hold one clock for edge-

triggered interrupt. EX1 is set if external interrupt is detected. And the EX1 is

automatically cleared during service routine fetch cycles for edge-triggered interrupts.

Timer Interrupts

Three interrupt request TF0, TF1 and TF2 are set by timer 0 ,timer 1 and timer 2 overflow.

TF0 and TF1 are cleared by hardware vectors and jump to interrupt service routine when

timer 0 and timer 1 interrupts are generated. TF2 is different to TF0/TF1. TF2 is clear by

software when timer 2 interrupt is generated.

The relative enable bit of Timre0, Timer1, Timer2 are ET0, ET1, and ET2 in register IE.

Timer 2 interrupts are generated by a logical OR of bits TF2 and EXF2 in register T2CON.

Neither flag is cleared by a hardware vector to a service routine. In fact, the interrupt

service routine must determine if TF2 or EXEF2 generated the interrupt, and then clear the

bit. Timer 2 interrupt is enabled by ET2 in register IE.

Serial Port Interrupt

Serial port interrupts are generated by the logical OR of bits RI and TI in the SCON register.

Neither flag is cleared by a hardware vector to the service routine. The service routine

resolves RI and TI interrupt generation and clears the serial port request flag. The serial

port interrupt is enabled by bit ES in the IE register. In the same way by using serial port 1.

Serial port 1 control register is SCON1, and the buffer is SBUF1. Here is one thing to be

noticed that serial port 1 only uses timer 1 to generate baud rate.