HT56R67 datasheet(66/104 Pages) HOLTEK

66 / 104 page

HT56R67/HT56R668/HT56C668/HT56R678/HT56C678/HT56R688

Rev. 1.20

March 4, 2010

Interrupts

Interrupts are an important part of any microcontroller

system. When an external event or an internal function

such as a Timer/Event Counter or an A/D converter re-

quires microcontroller attention, their corresponding in-

terrupt will enforce a temporary suspension of the main

program allowing the microcontroller to direct attention

to their respective needs. The device contains several

external interrupt and internal interrupts functions. The

external interrupts are controlled by the action of the ex-

ternal INT0, INT1 and PINT pins, while the internal inter-

rupts are controlled by the Timer/Event Counter

overflows, the Time Base interrupt, the RTC interrupt,

the SPI/I

2C interrupt and the the A/D converter interrupt.

Interrupt Registers

Overall interrupt control, which means interrupt enabling

and request flag setting, is controlled by the INTC0,

INTC1, and MFIC/MFIC0/MFIC1 registers, which are lo-

cated in the Data Memory. By controlling the appropriate

enable bits in these registers each individual interrupt

can be enabled or disabled. Also when an interrupt oc-

curs, the corresponding request flag will be set by the

microcontroller. The global enable flag if cleared to zero

will disable all interrupts.

Interrupt Operation

A Timer/Event Counter overflow, Time Base, RTC over-

flow, SPI/I

2C data transfer complete, an end of A/D con-

version or the external interrupt line being triggered will

all generate an interrupt request by setting their corre-

sponding request flag. When this happens and if their

appropriate interrupt enable bit is set, the Program

Counter, which stores the address of the next instruction

to be executed, will be transferred onto the stack. The

Program Counter will then be loaded with a new ad-

dress which will be the value of the corresponding inter-

rupt vector. The microcontroller will then fetch its next

instruction from this interrupt vector. The instruction at

this vector will usually be a JMP statement which will

jump to another section of program which is known as

the interrupt service routine. Here is located the code to

control the appropriate interrupt. The interrupt service

routine must be terminated with a RETI statement,

which retrieves the original Program Counter address

from the stack and allows the microcontroller to continue

with normal execution at the point where the interrupt

occurred.

The various interrupt enable bits, together with their as-

sociated request flags, are shown in the accompanying

diagram with their order of priority.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked, as the EMI bit will be cleared au-

tomatically. This will prevent any further interrupt nesting

from occurring. However, if other interrupt requests oc-

cur during this interval, although the interrupt will not be

immediately serviced, the request flag will still be re-

corded. If an interrupt requires immediate servicing

while the program is already in another interrupt service

routine, the EMI bit should be set after entering the rou-

tine, to allow interrupt nesting. If the stack is full, the in-

terrupt request will not be acknowledged, even if the

related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests,

the following table shows the priority that is applied.

Interrupt Source

Priority

Vector

External Interrupt 0

04H

External Interrupt 1

08H

Timer/Event Counter 0 Overflow

0CH

Timer/Event Counter 1 Overflow

10H

SPI/I2C Interrupt

14H

Multi-function Interrupt

18H

The A/D converter interrupt, Real Time clock interrupt,

Time Base interrupt and External Peripheral interrupt all

share the same interrupt vector which is 18H. Each of

these interrupts have their own own individual interrupt

flag but also share the same MFF interrupt flag. The

MFF flag will be cleared by hardware once the

Multi-function interrupt is serviced, however the individ-

ual interrupts that have triggered the Multi-function inter-

rupt need to be cleared by the application program.

External Interrupt

For an external interrupt to occur, the global interrupt

enable bit, EMI, and external interrupt enable bits, EEI0

and EEI1, must first be set. Additionally the correct

interrupt edge type must be selected using the

INTEDGE register to enable the external interrupt

function and to choose the trigger edge type. An actual

external interrupt will take place when the external

interrupt request flag, EIF0 or EIF1, is set, a situation

that will occur when a transition, whose type is chosen

by the edge select bit, appears on the INT0 or INT1 pin.

The external interrupt pins are pin-shared with the I/O

pins PD4 and PD5 and can only be configured as

external interrupt pins if their corresponding external

interrupt enable bit in the INTC0 register has been set.

The pin must also be setup as an input by setting the

corresponding PDC.4 and PDC.5 bits in the port control

full and the correct transition type appears on the

external interrupt pin, a subroutine call to the external

HT56R67 Datasheet(PDF) 66 Page - Holtek Semiconductor Inc

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