HT56R67 datasheet(72/104 Pages) HOLTEK

72 / 104 page

HT56R67/HT56R668/HT56C668/HT56R678/HT56C678/HT56R688

Rev. 1.20

March 4, 2010

Time Base Interrupt

The Time Base Interrupt is contained within the

Multi-function Interrupt.

For a Time Base Interrupt to be generated, the global in-

terrupt enable bit, EMI,Time Base Interrupt enable bit,

ETBI, and Multi-function interrupt enable bit, EMFI,

must first be set. An actual Time Base Interrupt will take

place when the Time Base Interrupt request flag, TBF, is

set, a situation that will occur when the Time Base over-

flows. When the interrupt is enabled, the stack is not full

and the Time Base overflows, a subroutine call to the

Multi-function interrupt vector at location18H, will take

place. When the Time Base Interrupt is serviced, the

EMI bit will be cleared to disable other interrupts, how-

ever only the MFF interrupt request flag will be reset. As

the TBF flag will not be automatically reset, it has to be

cleared by the application program.

The purpose of the Time Base function is to provide an

interrupt signal at fixed time periods. The Time Base in-

terrupt clock source originates from the Time Base inter-

rupt clock source originates from the internal clock

source fS. This fS input clock first passes through a di-

vider, the division ratio of which is selected by configura-

tion options to provide longer Time Base interrupt

periods. The Time Base interrupt time-out period ranges

from 2

12/f

S~2

15/f

S. The clock source that generates fS,

which in turn controls the Time Base interrupt period,

can originate from three different sources, the 32768Hz

oscillator, the 32K_INT internal oscillator or the System

oscillator/4, the choice of which is determine by the fS

clock source configuration option.

Essentially operating as a programmable timer, when

the Time Base overflows it will set a Time Base interrupt

flag which will in turn generate an Interrupt request via

the Multi-function Interrupt vector.

Programming Considerations

By disabling the interrupt enable bits, a requested inter-

rupt can be prevented from being serviced, however,

once an interrupt request flag is set, it will remain in this

condition in the INTC0, INTC1 and MFIC registers until

the corresponding interrupt is serviced or until the re-

quest flag is cleared by the application program.

It is recommended that programs do not use the

²CALL

subroutine

² instruction within the interrupt subroutine.

Interrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications. If

only one stack is left and the interrupt is not well con-

trolled, the original control sequence will be damaged

once a

²CALL subroutine² is executed in the interrupt

subroutine.

All of these interrupts have the capability of waking up

the processor when in the Power Down Mode.

Only the Program Counter is pushed onto the stack. If

the contents of the status or other registers are altered

by the interrupt service program, which may corrupt the

desired control sequence, then the contents should be

saved in advance.

f S S o u r c e

C o n f i g u r a t i o n

O p t i o n

f S Y S / 4

3 2 7 6 8 H z

3 2 K _ I N T

C o n f i g u r a t i o n O p t i o n

D i v i d e b y 2 1 2 ~ 2 1 5

f S

T i m e B a s e I n t e r r u p t

2 1 2 / f S ~ 2 1 5 / f S

Time Base Interrupt

R T C C R e g i s t e r

b 7

b 0

L V D O Q O S C L V D C

R T 2

R T 1

R T 0

R T 2

R T 1

R T 0

P e r i o d

2 8 / f S

2 9 / f S

2 1 0 / f S

2 1 1 / f S

2 1 2 / f S

2 1 3 / f S

2 1 4 / f S

2 1 5 / f S

R T C I n t e r r u p t P e r i o d

L o w V o l t a g e D e t e c t o r C o n t r o l

1 : e n a b l e

0 : d i s a b l e

R T C O s c i l l a t o r Q u i c k - s t a r t

1 : d i s a b l e

0 : e n a b l e

L o w V o l t a g e D e t e c t o r O u t p u t

1 : l o w v o l t a g e d e t e c t e d

0 : n o r m a l v o l t a g e

N o t i m p l e m e n t e d , r e a d a s " 0 "

Real Time Clock Control Register

- RTCC

HT56R67 Datasheet(PDF) 72 Page - Holtek Semiconductor Inc

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