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HT56R67 Datasheet(PDF) 82 Page - Holtek Semiconductor Inc |
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HT56R67 Datasheet(HTML) 82 Page - Holtek Semiconductor Inc |
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82 / 104 page ![]() HT56R67/HT56R668/HT56C668/HT56R678/HT56C678/HT56R688 Rev. 1.20 82 March 4, 2010 Low Voltage Detector - LVD The Low Voltage Detect internal function provides a means for the user to monitor when the power supply voltage falls below a certain fixed level as specified in the DC characteristics. LVD Operation The LVD function must be first enabled via a configura- tion option after which bits 3 and 5 of the RTCC register are used to control the overall function of the LVD. Bit 3 is the enable/disable control bit and is known as LVDC, when set low the overall function of the LVD will be dis- abled. Bit 5 is the LVD detector output bit and is known as LVDO. Under normal operation, and when the power supply voltage is above the specified VLVD value in the DC characteristic section, the LVDO bit will remain at a zero value. If the power supply voltage should fall below this VLVD value then the LVDO bit will change to a high value indicating a low voltage condition. Note that the LVDO bit is a read-only bit. By polling the LVDO bit in the RTCC register, the application program can therefore determine the presence of a low voltage condition. After power-on, or after a reset, the LVD will be switched off by clearing the LVDC bit in the RTCC register to zero. Note that if the LVD is enabled there will be some power consumption associated with its internal circuitry, how- ever, by clearing the LVDC bit to zero the power can be minimised. It is important not to confuse the LVD with the LVR function. In the LVR function an automatic reset will be generated by the microcontroller, whereas in the LVD function only the LVDO bit will be affected with no influence on other microcontroller functions. There are a range of voltage values, selected using a configuration option, which can be chosen to activate the LVD. Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown lo- cations, due to certain uncontrollable external events such as electrical noise. It operates by providing a de- vice reset when the Watchdog Timer counter overflows. Watchdog Timer Operation The Watchdog Timer clock source is provided by the in- ternal clock, fS, which is in turn supplied by one of two sources selected by configuration option: fSUB or fSYS/4. Note that if the Watchdog Timer configuration option has been disabled, then any instruction relating to its op- eration will result in no operation. Most of the Watchdog Timer options, such as en- able/disable, Watchdog Timer clock source and clear in- struction type are selected using configuration options. In addition to a configuration option to enable the Watch- dog Timer, there are four bits, WDTEN3~ WDTEN0, in the MISC register to offer an additional enable control of the Watchdog Timer. These bits must be set to a specific value of 1010 to disable the Watchdog Timer. Any other values for these bits will keep the Watchdog Timer en- abled. After power on these bits will have the disabled value of 1010. W D T S o u r c e C o n f i g u r a t i o n O p t i o n C o n t r o l L o g i c C L R W D T 1 F l a g C L R W D T 2 F l a g 1 o r 2 I n s t r u c t i o n s f S Y S / 4 W D T O s c i l l a t o r 8 - b i t D i v i d e r f S C L R W D T T i m e - o u t ( 2 1 3 / f S , 2 1 4 / f S , 2 1 5 / f S o r 2 1 6 / f S ) ¸ 2 7 - b i t P r e s c a l e r f S / 2 8 f S / 2 1 2 , f S / 2 1 3 , f S / 2 1 4 o r f S / 2 1 5 C o n f i g O p t i o n R T C O s c i l l a t o r Watchdog Timer M I S C R e g i s t e r b 7 W D T E N 0 b 0 W D T E N 1 P A 0 ~ P A 3 O p e n D r a i n C o n t r o l - d e s c r i b e d e l s e w h e r e W a t c h d o g T i m e r E n a b l e C o n t r o l O D E 0 W D T E N 3 1 W D T E N 2 W D T E N 3 O D E 1 O D E 2 O D E 3 W D T E N 2 0 W D T E N 1 1 W D T E N 0 0 d i s a b l e e n a b l e a l l o t h e r v a l u e s Watchdog Timer Software Control - MISC |
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