HT56R67 datasheet(23/104 Pages) HOLTEK

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HT56R67/HT56R668/HT56C668/HT56R678/HT56C678/HT56R688

Rev. 1.20

March 4, 2010

· AC is set if an operation results in a carry out of the

low nibbles in addition, or no borrow from the high nib-

ble into the low nibble in subtraction; otherwise AC is

cleared.

· Z is set if the result of an arithmetic or logical operation

is zero; otherwise Z is cleared.

· OV is set if an operation results in a carry into the high-

est-order bit but not a carry out of the highest-order bit,

or vice versa; otherwise OV is cleared.

· PDF is cleared by a system power-up or executing the

²CLR WDT² instruction. PDF is set by executing the

²HALT² instruction.

· TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is set by a

WDT time-out.

In addition, on entering an interrupt sequence or execut-

ing a subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status registers are important and if the subroutine

can corrupt the status register, precautions must be

taken to correctly save it.

Interrupt Control Registers

These 8-bit registers, INTC0, INTC1, MFIC, MFIC0,

MFIC1 and INTEDGE, control the operation of the device

interrupt functions. By setting various bits within these

registers using standard bit manipulation instructions, the

enable/disable function of each interrupt can be inde-

pendently controlled. A master interrupt bit within the

INTC0 register, the EMI bit, acts like a global enable/dis-

able and is used to set all of the interrupt enable bits on or

off. This bit is cleared when an interrupt routine is entered

to disable further interrupt and is set by executing the

²RETI² instruction. The INTEDGE register is used to se-

lect the active edges for the two external interrupt pins

INT0 and INT1.

Timer/Event Counter Registers

The devices contain several internal 8-bit and 16-bit

Timer/Event Counters, the actual amount depends upon

which device is selected. The registers TMR0, TMR1,

TMR2, TMR3 and the register pair TMR1L/TMR1H are

the locations where the timer values are located. These

registers can also be preloaded with fixed data to allow

different time intervals to be setup. The associated

control registers, TMR0C, TMR1C, TMR2C and TMR3C

contain the setup information for these timers, which

determines in what mode the timer is to be used as well

as containing the timer on/off control function.

Input/Output Ports and Control Registers

Within the area of Special Function Registers, the I/O

registers and their associated control registers play a

prominent role. All I/O ports have a designated register

correspondingly labeled as PA, PB, PC and PD. These

labeled I/O registers are mapped to specific addresses

within the Data Memory as shown in the Data Memory

table, which are used to transfer the appropriate output

or input data on that port. With each I/O port there is an

associated control register labeled PAC, PBC, PCC and

PDC, also mapped to specific addresses with the Data

Memory. The control register specifies which pins of that

port are set as inputs and which are set as outputs. To

setup a pin as an input, the corresponding bit of the con-

trol register must be set high, for an output it must be set

low. During program initialization, it is important to first

setup the control registers to specify which pins are out-

puts and which are inputs before reading data from or

writing data to the I/O ports. One flexible feature of these

registers is the ability to directly program single bits us-

ing the

²SET [m].i² and ²CLR [m].i² instructions. The

ability to change I/O pins from output to input and vice

versa by manipulating specific bits of the I/O control reg-

isters during normal program operation is a useful fea-

ture of these devices.

Pulse Width Modulator Registers

The devices contain multiple Pulse Width Modulator out-

puts each with their own related independent control reg-

ister pair, known as PWM0L/PWM0H, PWM1L/PWM1H,

PWM2L/PWM2H and PWM3L/PWM3H. The 12-bit con-

tents of each register pair, which defines the duty cycle

value for the modulation cycle of the Pulse Width Modula-

tor, along with an enable bit are contained in these regis-

ter pairs.

T O

P D F

O V

A C

S T A T U S R e g i s t e r

A r i t h m e t i c / L o g i c O p e r a t i o n F l a g s

C a r r y f l a g

A u x i l i a r y c a r r y f l a g

Z e r o f l a g

O v e r f l o w f l a g

S y s t e m M a n a g e m e n t F l a g s

P o w e r d o w n f l a g

W a t c h d o g t i m e - o u t f l a g

N o t i m p l e m e n t e d , r e a d a s " 0 "

b 7

b 0

Status Register

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