HT56R67 datasheet(42/104 Pages) HOLTEK

42 / 104 page

HT56R67/HT56R668/HT56C668/HT56R678/HT56C678/HT56R688

Rev. 1.20

March 4, 2010

Configuring the Timer Mode

In this mode, the Timer/Event Counter can be utilised to

measure fixed time intervals, providing an internal inter-

rupt signal each time the Timer/Event Counter over-

flows. To operate in this mode, the Operating Mode

Select bit pair, TnM1/TnM0, in the Timer Control Regis-

ter must be set to the correct value as shown.

Control Register Operating Mode

Select Bits for the Timer Mode

Bit7 Bit6

In this mode the internal clock, fSYS , is used as the inter-

nal clock for 8-bit Timer/Event Counter 0 and fSUB or

fSYS/4 is used as the internal clock for 16-bit Timer/Event

Counter 1. However, the clock source, fSYS, for the 8-bit

timer is further divided by a prescaler, the value of which

is determined by the Prescaler Rate Select bits

TnPSC2~TnPSC0, which are bits 2~0 in the Timer Con-

trol Register. After the other bits in the Timer Control

TnON, which is bit 4 of the Timer Control Register, can

be set high to enable the Timer/Event Counter to run.

Each time an internal clock cycle occurs, the

Timer/Event Counter increments by one. When it is full

and overflows, an interrupt signal is generated and the

Timer/Event Counter will reload the value already

loaded into the preload register and continue counting.

The interrupt can be disabled by ensuring that the

Timer/Event Counter Interrupt Enable bit in the corre-

sponding Interrupt Control Register, is reset to zero.

Configuring the Event Counter Mode

In this mode, a number of externally changing logic

events, occurring on the external timer pin, can be re-

corded by the Timer/Event Counter. To operate in this

mode, the Operating Mode Select bit pair, TnM1/TnM0,

in the Timer Control Register must be set to the correct

value as shown.

Control Register Operating Mode

Select Bits for the Event Counter Mode

Bit7 Bit6

In this mode, the external timer pin, is used as the

Timer/Event Counter clock source, however it is not di-

vided by the internal prescaler. After the other bits in the

Timer Control Register have been setup, the enable bit

TnON, which is bit 4 of the Timer Control Register, can

be set high to enable the Timer/Event Counter to run. If

the Active Edge Select bit, TnE, which is bit 3 of the

Timer Control Register, is low, the Timer/Event Counter

will increment each time the external timer pin receives

a low to high transition. If the Active Edge Select bit is

high, the counter will increment each time the external

timer pin receives a high to low transition. When it is full

and overflows, an interrupt signal is generated and the

Timer/Event Counter will reload the value already

loaded into the preload register and continue counting.

The interrupt can be disabled by ensuring that the

Timer/Event Counter Interrupt Enable bit in the corre-

sponding Interrupt Control Register, is reset to zero.

As the external timer pin is shared with an I/O pin, to en-

b 7

T n E

T n O N

T n M 0

T n M 1

b 0

T M R n C R e g i s t e r ( n = 1 )

N o t i m p l e m e n t e d , r e a d a s " 0 "

E v e n t C o u n t e r a c t i v e e d g e s e l e c t

1 : c o u n t o n f a l l i n g e d g e

0 : c o u n t o n r i s i n g e d g e

P u l s e W i d t h M e a s u r e m e n t a c t i v e e d g e s e l e c t

1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e

0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e

T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e

1 : e n a b l e

0 : d i s a b l e

T n M 1

T n M 0

n o m o d e a v a i l a b l e

e v e n t c o u n t e r m o d e

t i m e r m o d e

p u l s e w i d t h m e a s u r e m e n t m o d e

O p e r a t i n g m o d e s e l e c t

T i m e r c l o c k s o u r c e

1 : f S U B ( 3 2 7 6 8 H z o r 3 2 K R C )

0 : f S Y S / 4

T n S

Timer/Event Counter Control Register

- TMRnC

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N

T i m e r + N + 1

Timer Mode Timing Chart

HT56R67 Datasheet(PDF) 42 Page - Holtek Semiconductor Inc

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