MAC7200 datasheet(260/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

182

Freescale Semiconductor

11.11.4.1.2

Internal Watchpoint Units 3 - 6

Watchpoint units 3 - 6 can be enabled to assert on an instruction address compare. The two least significant

bits of the address are automatically masked for word accesses (ARM mode) and the least significant bit

is masked for half word accesses (thumb mode).

11.11.4.1.3

ARM7 Watchpoints

The ARM7 EmbeddedICE module is capable of setting up to two (2) address and/or data watchpoints.

Please refer to the debug chapter of the ARM7TDMI-S (Rev 4) Technical Reference Manual

(ARM DDI 0234A) for details on watchpoint initialization.

11.11.4.2 Processor Breakpoints

The ARM watchpoint units and the Nexus watchpoint units 3 - 6 can be used to assert a processor

breakpoint. If the processor is configured for halt mode, the processor will enter into debug state before

executing the instruction at the specified address.

11.11.4.3 Watchpoint Messaging (WPM)

The A7S Nexus3 module provides watchpoint messaging using the IEEE-ISTO 5001 defined TCODE.

Enabling watchpoint messaging is done by setting the watchpoint enable (WEN) bit in the DC register.

11.11.4.3.1

Watchpoint Message

When watchpoint messaging is enabled, and any of the eight (8) possible watchpoint sources asserts, a

watchpoint message will be sent to the queue to be transmitted. The message indicates which

watchpoint(s) asserted based on the encodings in Table 11-43.

Table 11-42. Internal Data Watchpoint Configuration Examples

Compare Operation

BWO

BWAM

BWDM

Compare Target

Single address only

010

FFFF FFFF

xxxx

BWA[31:0]

Address range only

010

FFFF FFF0

xxxx

BWA[31:4]

Signal address and word value

011

FFFF FFFF

1111

BWA[31:0] and BWD[31:0]

Word value only

001

xxxx xxxx

1111

BWD[31:0]

Signal address and byte value

011

FFFF FFFF

0001

BWA[31:0] and BWD[7:0]

0010

BWA[31:0] and BWD[15:8]

0100

BWA[31:0] and BWD[23:16]

1000

BWA[31:0] and BWD[31:24]

Single address and halfword value

011

FFFF FFFF

0011

BWA[31:0] and BWD[15:0]

1100

BWA[31:0] and BWD[31:24]

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