MAC7200 datasheet(298/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

220

Freescale Semiconductor

12.2.4.1.13

DMA Interrupt Request (DMAINTH, DMAINTL)

The DMAINT{H,L} registers provide a bit map for the implemented channels {16,32,64} signaling the

presence of an interrupt request for each channel. DMAINTH supports channels 63-32, while DMAINTL

covers channels 31-00. The dma_engine signals the occurrence of a programmed interrupt upon the

completion of a data transfer as defined in the transfer control descriptor by setting the appropriate bit in

this register. The outputs of this register are directly routed to the platform’s interrupt controller. During

the execution of the interrupt service routine associated with any given channel, it is software’s

responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the

DMACINT register in the interrupt service routine is used for this purpose.

The state of any given channel’s interrupt request is directly affected by writes to this register; it is also

affected by writes to the DMACINT register. On writes to the DMAINT, a one in any bit position clears

the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding

channel’s current interrupt status. The DMACINT register is provided so the interrupt request for a single

channel can easily be cleared without the need to perform a read-modify-write sequence to the

DMAINT{H,L} registers. See Figure 12-14 and Table 12-17 for the DMAINT definition.

0000000000000000

Reset

0000000000000000

9876543210

0000000000000000

Reset

0000000000000000

Reset

0000000000000000

9876543210

Reset

0000000000000000

= Unimplemented

Figure 12-14. DMA Interrupt Request (DMAINTH, DMAINTL) Registers

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