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6402 Datasheet(PDF) 171 Page - Intel Corporation |
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6402 Datasheet(HTML) 171 Page - Intel Corporation |
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171 / 250 page ![]() Intel® 6400/6402 Advanced Memory Buffer Datasheet 171 Registers 14.3.1.2 FBDS1: FBD Status 1 This register contains copies of status bits returned by the AMB in the most recent northbound status frame when SYNC command R[1:0] field is 2’b01. 14.3.1.3 FBDS2: FBD Status 2 This register contains copies of status bits returned by the AMB in the most recent northbound status frame when SYNC command R[1:0] field is 2’b10. 3RO 0h S3: Northbound Debug Event (1 = asserted, 0 = inactive): This bit is used to communicate debug events to the host. 2:1 RO 0h S[2:1]: Thermal Trip: This field indicates various thermal conditions of the AMB as follows: • 00 – Below TEMPLO • 01 – Above TEMPLO • 10 – Above TEMPMID and falling • 11 – Above TEMPMID and rising The TEMPLO threshold is generally used to inform the host to accelerate refresh events. The TEMPMID threshold is generally used to inform the host that a thermal limit has been exceeded and that thermal throttling is needed. Refer to the RAS chapter for more details on thermal management. 0 RO 0h S0: ERROR Asserted: This bit indicates an error has been detected by the AMB. Errors can be alert or other type. Device: NodeID Function: 1 Offset: 40h Bit Att r Default Description Device: NodeID Function: 1 Offset: 41h Bit Att r Default Description 7:5 RV 0h Reserved 4 RO 0h SP: Parity: This bit contains an odd parity bit that covers the S[3:0] field. 3:1 RV 0h Reserved 0 RO 0h S0: Data Merge Error: This bit indicates that the northbound data merge alignment logic of an intermediate AMB cannot met the timing required to merge its DRAM data into the northbound data stream when required. Refer to the initialization chapter for details. Device: NodeID Function: 1 Offset: 42h Bit Att r Default Description 7:5 RV 0h Reserved 4 RO 0h SP: Parity: This bit contains an odd parity bit that covers the S[3:0] field. 3:0 RV 0h Reserved |
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