3000 datasheet(68/102 Pages) INTEL

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Land Listing and Signal Descriptions

Dual-Core Intel® Xeon® Processor 3000 Series Datasheet

DEFER#

Input

DEFER# is asserted by an agent to indicate that a transaction cannot

be ensured in-order completion. Assertion of DEFER# is normally the

responsibility of the addressed memory or input/output agent. This

signal must connect the appropriate pins/lands of all processor FSB

agents.

DRDY#

Input/Output

DRDY# (Data Ready) is asserted by the data driver on each data

transfer, indicating valid data on the data bus. In a multi-common

clock data transfer, DRDY# may be de-asserted to insert idle clocks.

This signal must connect the appropriate pins/lands of all processor

FSB agents.

DSTBN[3:0]#

Input/Output

DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.

DSTBP[3:0]#

Input/Output

DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.

FCx

Other

FC signals are signals that are available for compatibility with other

processors.

FERR#/PBE#

Output

FERR#/PBE# (floating point error/pending break event) is a

multiplexed signal and its meaning is qualified by STPCLK#. When

STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error

and will be asserted when the processor detects an unmasked

floating-point error. When STPCLK# is not asserted, FERR#/PBE# is

similar to the ERROR# signal on the Intel 387 coprocessor, and is

included for compatibility with systems using MS-DOS*-type floating-

point error reporting. When STPCLK# is asserted, an assertion of

FERR#/PBE# indicates that the processor has a pending break event

waiting for service. The assertion of FERR#/PBE# indicates that the

processor should be returned to the Normal state. For additional

information on the pending break event functionality, including the

identification of support of the feature and enable/disable information,

refer to volume 3 of the Intel Architecture Software Developer's

Manual and the Intel Processor Identification and the CPUID

Instruction application note.

GTLREF[1:0]

Input

GTLREF[1:0] determine the signal reference level for GTL+ input

signals. GTLREF is used by the GTL+ receivers to determine if a signal

is a logical 0 or logical 1.

HIT#

HITM#

Input/Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop

operation results. Any FSB agent may assert both HIT# and HITM#

together to indicate that it requires a snoop stall, which can be

continued by reasserting HIT# and HITM# together.

IERR#

Output

IERR# (Internal Error) is asserted by a processor as the result of an

internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the processor FSB. This transaction may

optionally be converted to an external error signal (e.g., NMI) by

system core logic. The processor will keep IERR# asserted until the

assertion of RESET#.

This signal does not have on-die termination. Refer to Section 2.6.2

for termination requirements.

Table 4-3.

Signal Description (Sheet 3 of 7)

Name

Type

Description

Signals

Associated Strobe

D[15:0]#, DBI0#

DSTBN0#

D[31:16]#, DBI1#

DSTBN1#

D[47:32]#, DBI2#

DSTBN2#

D[63:48]#, DBI3#

DSTBN3#

Signals

Associated Strobe

D[15:0]#, DBI0#

DSTBP0#

D[31:16]#, DBI1#

DSTBP1#

D[47:32]#, DBI2#

DSTBP2#

D[63:48]#, DBI3#

DSTBP3#

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