3000 datasheet(70/102 Pages) INTEL

70 / 102 page

Land Listing and Signal Descriptions

Dual-Core Intel® Xeon® Processor 3000 Series Datasheet

REQ[4:0]#

Input/Output

REQ[4:0]# (Request Command) must connect the appropriate

pins/lands of all processor FSB agents. They are asserted by the

current bus owner to define the currently active transaction type.

These signals are source synchronous to ADSTB0#.

RESET#

Input

Asserting the RESET# signal resets the processor to a known state

and invalidates its internal caches without writing back any of their

contents. For a power-on Reset, RESET# must stay active for at least

one millisecond after VCC and BCLK have reached their proper

specifications. On observing active RESET#, all FSB agents will de-

assert their outputs within two clocks. RESET# must not be kept

asserted for more than 10 ms while PWRGOOD is asserted.

A number of bus signals are sampled at the active-to-inactive

transition of RESET# for power-on configuration. These configuration

options are described in the Section 6.1.

This signal does not have on-die termination and must be terminated

on the system board.

RESERVED

All RESERVED lands must remain unconnected. Connection of these

lands to VCC, VSS, VTT, or to any other signal (including each other)

can result in component malfunction or incompatibility with future

processors.

RS[2:0]#

Input

RS[2:0]# (Response Status) are driven by the response agent (the

agent responsible for completion of the current transaction), and must

connect the appropriate pins/lands of all processor FSB agents.

SKTOCC#

Output

SKTOCC# (Socket Occupied) will be pulled to ground by the processor.

System board designers may use this signal to determine if the

processor is present.

SMI#

Input

SMI# (System Management Interrupt) is asserted asynchronously by

system logic. On accepting a System Management Interrupt, the

processor saves the current state and enter System Management

Mode (SMM). An SMI Acknowledge transaction is issued, and the

processor begins program execution from the SMM handler.

If SMI# is asserted during the de-assertion of RESET#, the processor

will tri-state its outputs.

STPCLK#

Input

STPCLK# (Stop Clock), when asserted, causes the processor to enter

a low power Stop-Grant state. The processor issues a Stop-Grant

Acknowledge transaction, and stops providing internal clock signals to

all processor core units except the FSB and APIC units. The processor

continues to snoop bus transactions and service interrupts while in

Stop-Grant state. When STPCLK# is de-asserted, the processor

restarts its internal clock to all units and resumes execution. The

assertion of STPCLK# has no effect on the bus clock; STPCLK# is an

asynchronous input.

TCK

Input

TCK (Test Clock) provides the clock input for the processor Test Bus

(also known as the Test Access Port).

TDI

Input

TDI (Test Data In) transfers serial test data into the processor. TDI

provides the serial input needed for JTAG specification support.

TDO

Output

TDO (Test Data Out) transfers serial test data out of the processor.

TDO provides the serial output needed for JTAG specification support.

TESTHI[13:0]

Input

TESTHI[13:0] must be connected to the processor’s appropriate

power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal

description) through a resistor for proper processor operation. See

Section 2.5 for more details.

THERMDA

Other

Thermal Diode Anode. See Section 5.3.

THERMDC

Other

Thermal Diode Cathode. See Section 5.3.

Table 4-3.

Signal Description (Sheet 5 of 7)

Name

Type

Description

3000 Datasheet(PDF) 70 Page - Intel Corporation

3000 Datasheet(HTML) 70 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL