3000 datasheet(27/102 Pages) INTEL

27 / 102 page

Dual-Core Intel® Xeon® Processor 3000 Series Datasheet

Electrical Specifications

2.7.3.1

GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the

processor silicon. See Table 2-9 for details on which GTL+ signals do not include on-die

termination.

Valid high and low levels are determined by the input buffers by comparing with a

reference voltage called GTLREF. Table 2-15 lists the GTLREF specifications. The GTL+

reference voltage (GTLREF) should be generated on the system board using high

precision voltage divider circuits.

2.7.4

Clock Specifications

2.7.5

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the processor’s core frequency is a

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its

default ratio during manufacturing. Refer to Table 2-16 for the processor supported

ratios.

The processor uses a differential clocking implementation. For more information on the

processor clocking, contact your Intel Field representative. Platforms using a CK505

Clock Synthesizer/Driver should comply with the specifications in Section 2.7.8.

Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications

in Section 2.7.9.

Table 2-15. GTL+ Bus Voltage Definitions

Symbol

Parameter

Min

Typ

Max

Units

Notes1

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

GTLREF_PU

GTLREF pull up resistor on

Mukilteo-2 (3000/3010) chipset

family boards

124 * 0.99

124

124 * 1.01

2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each GTLEREF land).

Refer to the applicable platform design guide for implementation details.

GTLREF_PD

GTLREF pull down resistor on

Mukilteo-2 (3000/3010) chipset

family boards

210 * 0.99

210

210 * 1.01

GTLREF_PU

GTLREF pull up resistor on

Bearlake chipset family boards

100 * 0.99

100

100 * 1.01

GTLREF_PD

GTLREF pull down resistor on

Bearlake chipset family boards

200 * 0.99

200

200 * 1.01

RTT

Termination Resistance

3. RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver. Refer to the appropriate

platform design guide for the board impedance. Refer to processor I/O buffer models for I/V characteristics.

COMP[3:0]

COMP Resistance

49.40

49.90

50.40

4. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design

guide for implementation details. COMP[3:0] and COMP8 resistors are to VSS.

COMP8

COMP Resistance

24.65

24.90

25.15

3000 Datasheet(PDF) 27 Page - Intel Corporation

3000 Datasheet(HTML) 27 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL