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N270 Datasheet(PDF) 24 Page - Intel Corporation |
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N270 Datasheet(HTML) 24 Page - Intel Corporation |
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24 / 57 page ![]() Electrical Specifications 24 Datasheet 3.7 FSB Signal Groups To simplify the following discussion, the FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 5 identifies which signals are common clock, source synchronous, and asynchronous. Table 5. FSB Pin Groups Signal Group Type Signals1 AGTL+ Common Clock Input Synchronous to BCLK [1:0] BPRI#, DEFER#, PREQ#4, RESET#, RS [2:0]#, TRDY#, DPWR# AGTL+ Common Clock I/O Synchronous to BCLK [1:0] ADS#, BNR#, BPM [3:0]#, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY# AGTL+ Source Synchronous I/O Synchronous to assoc. strobe Signals Associated Strobe REQ [4:0]#, A [16:3]# ADSTB0# A [31:17]# ADSTB1# D [15:0]# DSTBP0#, DSTBN0# D [31:16]# DSTBP1#, DSTBN1# D [47:32]# DSTBP2#, DSTBN2# D [63:48]# DSTBP3#, DSTBN3 # AGTL+ Strobes Synchronous to BCLK [1:0] ADSTB [1:0]#, DSTBP [3:0]#, DSTBN [3:0]# CMOS Input Asynchronous DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/ NMI, PWRGOOD, SMI#, SLP#, STPCLK# Open Drain Output Asynchronous FERR#, THERMTRIP#, IERR# Open Drain I/O Asynchronous PROCHOT#3 CMOS Output Asynchronous VID [6:0], BSEL [2:0] CMOS Input Synchronous to TCK TCK, TDI, TMS, TRST# |
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