N270 datasheet(48/57 Pages) INTEL

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Package Mechanical Specifications and Pin Information

Datasheet

Signal Name

Type

Description

TDO

TDO (Test Data Out) transfers serial test data out of the

processor. TDO provides the serial output needed for JTAG

specification support. Please contact your Intel representative for

more implementation details.

TEST[1:4]

Refer to the appropriate platform design guide for further TEST1,

TEST2, TEST3, and TEST4 termination requirements and

implementation details. All TEST signals can be left as No

Connects.

THRMTRIP#

The processor protects itself from catastrophic overheating by

use of an internal thermal sensor. This sensor is set well above

the normal operating temperature to ensure that there are no

false trips. The processor will stop all execution when the junction

temperature exceeds approximately 125°C. This condition is

signaled to the system by the THERMTRIP# (Thermal Trip) pin.

For termination requirements, please contact your Intel

representative for more implementation details.

THRMDA

PWR

Thermal Diode - Anode

THRMDC

PWR

Thermal Diode - Cathode

TMS

TMS (Test Mode Select) is a JTAG specification support signal

used by debug tools. Please contact your Intel representative for

more implementation details.

TRDY#

TRDY# (Target Ready) is asserted by the target to indicate that it

is ready to receive a write or implicit writeback data transfer.

TRDY# must connect the appropriate pins of both FSB agents.

TRST#

TRST# (Test Reset) resets the Test Access Port (TAP) logic.

TRST# must be driven low during power on Reset. Please contact

your Intel representative for more implementation details.

VCCA

PWR

VCCA provides isolated power for the internal processor core

PLLs. Please contact your Intel representative for more

implementation details.

VCC

PWR

Processor core power supply

VSS

GND

Processor core ground node.

VSS / NCTF

GND

Non Critical to Function

VID [6:0]

VID [6:0] (Voltage ID) pins are used to support automatic

selection of power supply voltages (VCC). Unlike some previous

generations of processors, these are CMOS signals that are

driven by the processor. The voltage supply for these pins must

be valid before the VR can supply VCC to the processor.

Conversely, the VR output must be disabled until the voltage

supply for the VID pins becomes valid. The VID pins are needed

to support the processor voltage specification variations. See

Table 3 for definitions of these pins. The VR must supply the

voltage that is requested by the pins, or disable itself.

VCCP

PWR

Processor I/O Power Supply

N270 Datasheet(PDF) 48 Page - Intel Corporation

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