AM3894 datasheet(13/299 Pages) TI

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AM3894

AM3892

www.ti.com

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

2.5.1.1

Mailbox Registers

Table 2-3 lists the Mailboxes available on this device. The register set below is applicable to these

mailboxes. Table 2-4 lists the Mailbox registers.

Table 2-3. Mailboxes

MAILBOX TYPE

USER NUMBER (u)

MAILBOX NUMBER (m)

MESSAGES PER MAILBOX

System Mailbox

0 to 3

0 to 11

Table 2-4. Mailbox Registers Summary(1)

HEX ADDRESS

ACRONYM

0x480C 8000

MAILBOX_REVISION

Mailbox Revision

0x480C 8010

MAILBOX_SYSCONFIG

Mailbox System Configuration

0x480C 8040 + (0x4 * m)

MAILBOX_MESSAGE_m

Mailbox Message

0x480C 8080 + (0x4 * m)

MAILBOX_FIFOSTATUS_m

Mailbox FIFO Status

0x480C 80C0 + (0x4 * m)

MAILBOX_MSGSTATUS_m

Mailbox Message Status

0x480C 8100 + (0x10 * u)

MAILBOX_IRQSTATUS_RAW_u Mailbox IRQ RAW Status

0x480C 8104 + (0x10 * u)

MAILBOX_IRQSTATUS_CLR_u

Mailbox IRQ Clear Status

0x480C 8108 + (0x10 * u)

MAILBOX_IRQENABLE_SET_u

Mailbox IRQ Enable Set

0x480C 810C + (0x10 * u)

MAILBOX_IRQENABLE_CLR_u

Mailbox IRQ Enable Clear

0x480C 8140

Reserved

(1)

For the range of m and u, see Table 2-3.

2.5.2

Spinlock Module

The Spinlock module provides hardware assistance for synchronizing the processes running on multiple

processors in the device:

•

ARM Cortex-A8 processor

•

Media Controller processors.

The Spinlock module implements 64 spinlocks (or hardware semaphores) that provide an efficient way to

perform a lock operation of a device resource using a single read-access, avoiding the need for a

read-modify-write bus transfer of which the programmable cores are not capable.

2.5.2.1

Spinlock Registers

Table 2-5. Spinlock Registers Summary(1)

HEX ADDRESS

ACRONYM

0x480C A000

SPINLOCK_REV

Revision

0x480C A010h

SPINLOCK_SYSCFG

System Configuration

0x480C A014h

SPINLOCK_SYSSTAT

System Status

0x480C A800 + (0x4*i)

SPINLOCK_LOCK_REG_i

Lock

(1)

i = 0 to 63

2.6

Power, Reset and Clock Management (PRCM) Module

The PRCM module is the centralized management module for the power, reset, and clock control signals

of the device. It interfaces with all the components on the device for power, clock, and reset management

through power-control signals. It integrates enhanced features to allow the device to adapt energy

consumption dynamically, according to changing application and performance requirements. The

innovative hardware architecture allows a substantial reduction in leakage current.

The PRCM module is composed of two main entities:

Device Overview

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