AM3871 datasheet(146/345 Pages) TI1

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AM3874, AM3872, AM3871

SPRS695

– SEPTEMBER 2011

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4.3

Pin Multiplexing Control

Device level pin multiplexing is controlled on a pin-by-pin basis by the MUXMODE bits of the PINCNTL1

–

PINCNTL270 registers in the Control Module.

Pin multiplexing selects which one of several peripheral pin functions controls the pin's I/O buffer output

data values. Table 4-11 shows the peripheral pin functions associated with each MUXMODE setting for all

multiplexed pins. The default pin multiplexing control for almost every pin is to select MUXMODE = 0x0, in

which case the pin's I/O buffer is 3-stated.

In most cases, the input from each pin is routed to all of the peripherals that share the pin, regardless of

the MUXMODE setting. However, in some cases a constant "0" or "1" value is routed to the associated

peripheral when its peripheral function is not selected to control any output pin. For more details on the

De-Selected Input State (DSIS), see the "MUXED" columns of each Terminal Functions table (Section 3.2,

Terminal Functions).

Some peripheral pin functions can be routed to more than one device pin. These types of peripheral pin

functions are called Multimuxed (MM) and may have different Switching Characteristics and Timing

Requirements for each device pin option. The Multimuxed peripheral pin functions are labeled as "MM" in

Terminal Functions tables in Section 3.2, Terminal Functions and the associated timings for each MM pin

option are in Section 8, Peripheral Information and Timings.

(1) "(M0)" represents multimuxed option "0" for this pin function, "(M1)" represents multimuxed option "1" for this pin function, ... etc.

(2) Within this MUXMODE setting, EMAC[x] GMII or RGMII pin functions are selected via the RGMII0_EN and/or RGMII1_EN bits (8 and 9,

respectively) in the GMII_SEL register [0x4814_0650] of the Control Module. "0" = GMII (default) and "1" = RGMII.

146

Device Configurations

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AM3871 Datasheet(PDF) 146 Page - Texas Instruments