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AM1802 Datasheet(PDF) 172 Page - Texas Instruments |
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AM1802 Datasheet(HTML) 172 Page - Texas Instruments |
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172 / 180 page  TCK TDO 1 7 2 3 RTCK 4 5 6 9 8 TDI/TMS/TRST AM1802 SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012 www.ti.com Table 5-99. JTAG ID Register Selection Bit Descriptions BIT NAME DESCRIPTION 31:28 VARIANT Variant (4-Bit) value 27:12 PART NUMBER Part Number (16-Bit) value 11-1 MANUFACTURER Manufacturer (11-Bit) value 0 LSB LSB. This bit is read as a "1". 5.24.4.2 JTAG Test-Port Electrical Data/Timing Table 5-100. Timing Requirements for JTAG Test Port (see Figure 5-58) 1.2V 1.1V 1.0V No. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tc(TCK) Cycle time, TCK 40 50 66.6 ns 2 tw(TCKH) Pulse duration, TCK high 16 20 26.6 ns 3 tw(TCKL) Pulse duration, TCK low 16 20 26.6 ns 4 tc(RTCK) Cycle time, RTCK 40 50 66.6 ns 5 tw(RTCKH) Pulse duration, RTCK high 16 20 26.6 ns 6 tw(RTCKL) Pulse duration, RTCK low 16 20 26.6 ns 7 tsu(TDIV-RTCKH) Setup time, TDI/TMS/TRST valid before RTCK high 4 4 4 ns 8 th(RTCKH-TDIV) Hold time, TDI/TMS/TRST valid after RTCK high 4 6 8 ns Table 5-101. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see Figure 5-58) 1.2V 1.1V 1.0V No. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 9 td(RTCKL-TDOV) Delay time, RTCK low to TDO valid 18 23 31 ns Figure 5-58. JTAG Test-Port Timing 5.24.5 JTAG 1149.1 Boundary Scan Considerations To use boundary scan, the following sequence should be followed: • Execute a valid reset sequence and exit reset • Wait at least 6000 OSCIN clock cycles • Enter boundary scan mode using the JTAG pins No specific value is required on the EMU0 and EMU1 pins for boundary scan testing. If TRST is not driven by the boundary scan tool or tester, TRST should be externally pulled high during boundary scan testing. 172 Peripheral Information and Electrical Specifications Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1802 |
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