AM1802 datasheet(167/180 Pages) TI1

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AM1802

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SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012

5.24.1 JTAG Port Description

The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,

TDI, and TDO), a return clock (RTCK) due to the clocking requirements of the ARM926EJ-S and

emulation signals EMU0 and EMU1. TRST holds the debug and boundary scan logic in reset when pulled

low (its default state). Since TRST has an internal pull-down resistor, this ensures that at power up the

device functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST

should be driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be

performed while the TRST pin is pulled low.

Table 5-96. JTAG Port Description

TYPE

NAME

DESCRIPTION

When asserted (active low) causes all test and debug logic in the device to be reset

TRST

Test Logic Reset

along with the IEEE 1149.1 interface

This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic.

TCK

Test Clock

Depending on the emulator attached to , this is a free running clock or a gated clock

depending on RTCK monitoring.

Synchronized TCK. Depending on the emulator attached to, the JTAG signals are

RTCK

Returned Test Clock

clocked from RTCK or RTCK is monitored by the emulator to gate TCK.

TMS

Test Mode Select

Directs the next state of the IEEE 1149.1 test access port state machine

TDI

Test Data Input

Scan data input to the device

TDO

Test Data Output

Scan data output of the device

EMU0

I/O

Emulation 0

Channel 0 trigger + HSRTDX

EMU1

I/O

Emulation 1

Channel 1 trigger + HSRTDX

5.24.2 Scan Chain Configuration Parameters

Table 5-97 shows the TAP configuration details required to configure the router/emulator for this device.

Table 5-97. JTAG Port Description

Router Port ID

Default TAP

TAP Name

Tap IR Length

Reserved

ARM926

ETB

The router is revision C and has a 6-bit IR length.

5.24.3 Initial Scan Chain Configuration

The first level of debug interface that sees the scan controller is the TAP router module. The debugger

can configure the TAP router for serially linking up to 16 TAP controllers or individually scanning one of

the TAP controllers without disrupting the IR state of the other TAPs.

5.24.3.1 Adding TAPS to the Scan Chain

The TAP router must be programmed to add additional TAPs to the scan chain. The following JTAG scans

must be completed to add the ARM926EJ-S to the scan chain.

A Power-On Reset (POR) or the JTAG Test-Logic Reset state configures the TAP router to contain only

the router’s TAP.

Peripheral Information and Electrical Specifications

167

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