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RM48L930 Datasheet(PDF) 129 Page - Texas Instruments

Part # RM48L930
Description  RM48Lx30 16/32-Bit RISC Flash Microcontroller
PDF  147 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

RM48L930 Datasheet(HTML) 129 Page - Texas Instruments

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SDA
SCL
t
w(SDAH)
t
w(SCLL)
t
w(SCLH)
t
w(SP)
t
h(SCLL-SDAL)
t
h(SDA-SCLL)
t
h(SCLL-SDAL)
t
su(SCLH-SDAL)
t
f(SCL)
t
c(SCL)
t
r(SCL)
t
su(SCLH-SDAH)
Stop
Start
Repeated Start
Stop
t
su(SDA-SCLH)
RM48L930
RM48L730
RM48L530
www.ti.com
SPNS176
– SEPTEMBER 2011
5.8.2
I2C I/O Timing Specifications
Table 5-14. I2C Signals (SDA and SCL) Switching Characteristics(1)
Parameter
Standard Mode
Fast Mode
Unit
MIN
MAX
MIN
MAX
tc(I2CCLK)
Cycle time, Internal Module clock for I2C,
75.2
149
75.2
149
ns
prescaled from VCLK
tc(SCL)
Cycle time, SCL
10
2.5
ms
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
4.7
0.6
ms
repeated START condition)
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated
4
0.6
ms
START condition)
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
ms
tw(SCLH)
Pulse duration, SCL high
4
0.6
ms
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
250
100
ns
th(SDA-SCLL)
Hold time, SDA valid after SCL low (for I2C bus
0
3.45(2)
0
0.9
ms
devices)
tw(SDAH)
Pulse duration, SDA high between STOP and
4.7
1.3
ms
START conditions
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP
4.0
0.6
ms
condition)
tw(SP)
Pulse duration, spike (must be suppressed)
0
50
ns
Cb
(3)
Capacitive load for each bus line
400
400
pF
(1)
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2)
The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
(3)
Cb = The total capacitance of one bus line in pF.
Figure 5-8. I2C Timings
Copyright
© 2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
129
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