AD7719 datasheet(13/40 Pages) AD

13 / 40 page

REV. 0

AD7719

–13–

Both Channels

The operation of the AUX channel is identical to the Main

channel with the exception that there is no PGA on the AUX

channel. The input chopping is incorporated into the input

multiplexer while the output chopping is accomplished by an

XOR gate at the output of the modulator. The chopped modu-

lator bit stream is applied to a Sinc

3 filter. The programming of

the Sinc

3 decimation factor is restricted to an 8-bit register SF,

the actual decimation factor is the register value times 8. The

decimated output rate from the Sinc

3 filter (and the ADC con-

version rate) will therefore be:

ADC

MOD

=×









where

fADC is the ADC update rate.

SF is the decimal equivalent of the word loaded to the

filter register.

fMOD is the modulator sampling rate of 32.768 kHz.

Programming the filter register determines the update rate for

both the main and aux ADC. Both ADCs operate with the same

update rate.

The chop rate of the channel is half the output data rate.

The frequency response of the filter H (f) is as follows:

f f

MOD

OUT

×× ×









××









sin (

)

sin (

)

sin (

)

sin (

)

where

fMOD = 32,768 Hz

SF = value programmed into SF SFR.

fOUT = fMOD/(SF

× 8 × 3)

The following shows plots of the filter frequency response for

the SF words shown in Table I. The overall frequency response

is the product of a Sinc

3 and a sinc response. There are Sinc3

notches at integer multiples of 3

× fADC and there are sinc notches

SINC3 FILTER

MUX

S-D

MOD1

XOR

ANALOG

INPUT

DIGITAL

OUTPUT

SF )

AIN + VOS

AIN – VOS

fCHOP

fMOD

fCHOP

fADC

(

)

Figure 5. Auxiliary ADC Channel Block Diagram

at odd integer multiples of fADC/2. The 3 dB frequency for all

values of SF obeys the following equation:

f (3 dB) = 0.24

× fADC

The signal chain is chopped as shown in Figures 4 and 5. The

chop frequency is:

CHOP

ADC

= 







As shown in the block diagram, the Sinc

3 filter outputs alternately

contain +VOS and –VOS, where VOS is the respective channel

offset. This offset is removed by performing a running average

of 2. This average by 2 means that the settling time to any change

in programming of the ADC will be twice the normal conversion

time, while an asynchronous step change on the analog input will

not be fully reflected until the third subsequent output.

SETTLE

ADC









=×

The allowable range for SF is 13 to 255, with a default of 69

(45H). The corresponding conversion rates, conversion times

and settling times are tabulated in Table I. Note that the con-

version time increases by 0.732 ms for each increment in SF.

Table I. ADC Conversion and Settling Times for Various

SF Words

Data Update Rate

Settling Time

Word

fADC (Hz)

tSETTLE (ms)

105.3

19.04

69 (Default)

19.79

101.07

255

5.35

373.54

Normal-mode rejection is the major function of the digital filter

on the AD7719. The normal mode 50

± 1 Hz rejection with an SF

word of 82 is typically –100 dB. The 60

± 1 Hz rejection with

SF = 68 is typically –100 dB. Simultaneous 50 Hz and 60 Hz

rejection of better than 60 dB is achieved with an SF of 69.

Choosing an SF word of 69 places notches at both 50 Hz and

60 Hz. Figures 6 to 9 show the filter rejection for a selection

of SF words.

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