REV. 0

AD7719

–21–

Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On-Reset = 00 Hex)

The Mode Register is an 8-bit register from which data can be read or to which data can be written. This register configures the

operating modes of the AD7719. Table XII outlines the bit designations for the Mode Register. MR7 through MR0 indicate the bit

location, MR denoting the bits are in the Mode Register. MR7 denotes the first bit of the data stream. The number in brackets indi-

cates the power-on/reset default status of that bit.

Table XII. MODE Register Bit Designations

Bit

Bit

Location

Name

Description

MR7

0

Reserved for Future Use.

MR6

BUF

Configures the Main ADC for buffered or unbuffered mode of operation. If set, the Main ADC

operates in unbuffered mode, lowering the power consumption of the AD7719. If cleared, the

Main ADC operates in buffered mode allowing the user to place source impedances on the front end

without contributing gain errors to the system.

MR5

0

Reserved for Future Use.

MR4

CHCON

Channel Configure Bit. If this bit is set, the Main ADC operates with three pseudo-differential input

channels and the AUX ADC does not have AIN3/AIN4 as an input option. If cleared, the Main

ADC operates with two fully differential input channels and the aux channel operates as one fully

differential input and two single-ended inputs or three single-ended inputs.

MR3

OSCPD

Oscillator Power-Down Bit.

If this bits is set, placing the AD7719 in standby mode will stop the crystal oscillator, reducing the

power drawn by the AD7719 to a minimum. The oscillator will require 300 ms to begin oscillating

when the ADC is taken out of standby mode. If this bit is cleared, the oscillator is not shut off when

the ADC is put into standby mode and will not require the 300 ms start-up time when the ADC is

taken out of standby.

MR2–MR0

MD2–MD0

Main and Aux ADC Mode Bits.

These bits select the operational mode of the enabled ADC as follows:

MD2

MD1

MD0

0

0

0

Power-Down Mode (Power-On Default).

The current sources, power switches, and PLL are shut off in power-down mode.

0

0

1

Idle Mode.

In Idle Mode the ADC filter and modulator are held in a reset state although the modulator clocks

are still provided.

0

1

0

Single Conversion Mode.

In Single Conversion Mode, a single conversion is performed on the enabled channels. On completion

of the conversion the ADC data registers are updated, the relevant flags in the STATUS register are

written and idle mode is entered with the MD2–MD0 being written accordingly to 001.

0

1

1

Continuous Conversion.

In continuous conversion mode the ADC data registers are regularly updated at the selected update

rate (see Filter register)

1

0

0

Internal Zero-Scale Calibration.

Internal short automatically connected to the enabled channel(s). Returns to Idle mode (001) when

complete.

1

0

1

Internal Full-Scale Calibration.

when complete.

1

1

0

System Zero-Scale Calibration.

User should connect system zero-scale input to the channel input pins as selected by CH1/CH0 and

ACH1/ACH0 bits in the control registers.

1

1

1

System Full-Scale Calibration.

User should connect system full-scale input to the channel input pins as selected by CH1/CH0 and

ACH1/ACH0 bits in the control registers.

MR7

MR6

MR5

MR4

MR3

MR2

MR1

MR0

0 (0)

BUF (0)

0 (0)

CHCON (0)

OSCPD (0)

MD2 (0)

MD1 (0)

MD0 (0)