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AD7719

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AD7719-to-68HC11 Interface

Figure 12 shows an interface between the AD7719 and the 68HC11

microcontroller. The diagram shows the minimum (3-wire) inter-

face with

CS on the AD7719 hard-wired low. In this scheme,

the RDY bits of the Status Register are monitored to determine

when the Data Register is updated. RDY0 indicates the status of

the Main ADC channel while RDY1 indicates the status of the

Aux channel. An alternative scheme, which increases the number

of interface lines to four, is to monitor the

RDY output line

from the AD7719. The monitoring of the

RDY line can be done in

two ways. First,

RDY can be connected to one of the 68HC11’s

port bits (such as PC0), which is configured as an input. This

port bit is then polled to determine the status of

RDY. The

second scheme is to use an interrupt driven system, in which case

the

RDY output is connected to the IRQ input of the 68HC11. For

interfaces that require control of the

CS input on the AD7719,

one of the port bits of the 68HC11 (such as PC1), which is

configured as an output, can be used to drive the

CS input.

The 68HC11 is configured in the master mode with its CPOL

bit set to a Logic 1 and its CPHA bit set to a Logic 1. When the

68HC11 is configured like this, its SCLK line idles high between

data transfers. The AD7719 is not capable of full duplex opera-

tion. If the AD7719 is configured for a write operation, no data appears

on the DOUT lines even when the SCLK input is active. Simi-

larly, if the AD7719 is configured for a read operation, data

presented to the part on the DIN line is ignored even when

SCLK is active.

68HC11

AD7719

VDD

SCK

MISO

MOSI

RESET

SCLK

DIN

DOUT

VDD

Figure 12. AD7719-to-68HC11 Interface

AD7719-to-8051 Interface

An interface circuit between the AD7719 and the 8XC51 microcon-

troller is shown in Figure 13. The diagram shows the minimum

number of interface connections with

CS on the AD7719 hard-

wired low. In the case of the 8XC51 interface, the minimum

number of interconnects is just two. In this scheme, the RDY

bits of the Status Register are monitored to determine when the

Data Register is updated. The alternative scheme, which increases

the number of interface lines to three, is to monitor the

RDY output

line from the AD7719. The monitoring of the

RDY line can be

done in two ways. First,

RDY can be connected to one of the

8XC51’s port bits (such as P1.0) which is configured as an input.

This port bit is then polled to determine the status of

RDY.

DVDD

8XC51

AD7719

P3.0

P3.1

RESET

SCLK

DVDD

10k

DIN

DOUT

Figure 13. AD7719-to-8XC51 Interface

The second scheme is to use an interrupt-driven system, in which

case the

RDY output is connected to the INT1 input of the

8XC51. For interfaces that require control of the

CS input on

the AD7719, one of the port bits of the 8XC51 (such as P1.1),

which is configured as an output, can be used to drive the

input. The 8XC51 is configured in its Mode 0 serial interface

mode. Its serial interface contains a single data line. As a result,

the DOUT and DIN pins of the AD7719 should be connected

together with a 10 k

Ω pull-up resistor. The serial clock on the

8XC51 idles high between data transfers. The 8XC51 outputs

the LSB first in a write operation, while the AD7719 expects the

MSB first so the data to be transmitted has to be rearranged

before being written to the output serial register. Similarly, the

AD7719 outputs the MSB first during a read operation while

the 8XC51 expects the LSB first. Therefore, the data read into

the serial buffer needs to be rearranged before the correct data

word from the AD7719 is available in the accumulator.

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