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AD7719

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Reference Detect

The AD7719 includes on-chip circuitry to detect if the part has

a valid reference on the main ADC for conversions or calibrations.

If the voltage between the external REFIN1(+) and REFIN1(–)

pins goes below 0.3 V or either the REFIN1(+) or REFIN1(–)

inputs are open circuit, the AD7719 detects that it no longer

has a valid reference. In this case, the NOXREF bit of the STA-

TUS register is set to a 1. If the AD7719 is performing normal

conversions and the NOXREF bit becomes active, the conver-

sion results revert to all 1s. Therefore, it is not necessary to

continuously monitor the status of the NOXREF bit when

performing conversions. It is only necessary to verify its sta-

tus if the conversion result read from the ADC Data Register

is all 1s. If the AD7719 is performing either an offset or gain

calibration and the NOXREF bit becomes active, the updating

of the respective calibration registers is inhibited to avoid

loading incorrect coefficients to these registers, and the ERR0

bit in the STATUS register is set. If the user is concerned

about verifying that a valid reference is in place every time a

calibration is performed, the status of the ERR0 bit should be

checked at the end of the calibration cycle.

Reset Input

The

RESET input on the AD7719 resets all the logic, the digi-

tal filter, and the analog modulator while all on-chip registers are

reset to their default state.

RDY is driven high and the AD7719

ignores all communications to any of its registers while the

RESET input is low. When the RESET input returns high, the

AD7719 operates with its default setup conditions and it is

necessary to set up all registers and carry out a system calibra-

tion if required after a

RESET command.

Power-Down Mode

Loading 0, 0, 0 to the MD2, MD1, MD0 bits in the ADC mode

power-down mode is the default condition for the AD7719 on

power-up. Individual ADCs (main or auxiliary) can be put in

power-down mode using the AD0EN in the main ADC control

in the auxiliary ADC control register (AD1CON) to power off

the auxiliary ADC. The AD7719 retains the contents of all its

on-chip registers (including the data register) while in power-

down or ADC disable mode.

The device power-down mode does not affect the digital inter-

face, and it does affect the status of the

RDY pin. Putting the

AD7719 into power-down or idle mode will reset the

RDY line

high. Placing the part in power-down mode, reduces the total

current (AIDD + DIDD) to 31

µA max when the part is operated

a 5 V and the oscillator allowed to run during power-down mode.

With the oscillator shut down, the total IDD is 3

µA max at 3 V

and 9

µA max at 5 V.

Idle Mode

The AD7719 also contains an idle mode. The ADC defaults

to this mode on completion of a calibration sequence and on

the completion of a conversion when operating in single con-

version mode. In idle mode the power consumption of the

AD7719 is not reduced below the normal mode dissipation.

ADC Disable Mode

This mode is entered by setting both the AD0EN and AD1EN

bits in the Main and Max ADC control registers to 0 and set-

ting the Mode bits (MD2, MD1, MD0) in the Mode register to

non-0. In this Mode the internal PLL is enabled and the user

can activate the current sources and power switches but the

power consumption of the ADC is reduced as both ADCs are

disabled. In this mode the AIDD is reduced to 0.15 mA and the

DIDD is reduced to 0.35 mA max at 3 V and to 0.4 mA max with

DVDD = 5 V.

Calibration

The AD7719 provides four calibration modes that can be pro-

grammed via the mode bits in the mode register. One of the

major benefits of the AD7719 is that it is factory- calibrated as

part of the final test process with the generated coefficients

stored within the ADC. At power-on, the factory gain calibra-

tion coefficients are automatically loaded to the gain calibration

registers on the AD7719. Each ADC (primary and auxiliary) has

dedicated calibration register pairs as outlined in the AD0CON

and AD1CON register descriptions. Given that the ADC is

factory-calibrated and a chopping scheme is employed that gives

excellent offset and drift performance, it is envisaged that in the

majority of applications the user will not need to perform any

field calibrations.

However, the factory calibration values in the ADC calibration

registers will be overwritten if any one of the four calibration

options are initiated. Even though an internal offset calibration

mode is described below, it should be recognized that both

ADCs are chopped. This chopping scheme inherently minimizes

offset and means that an internal offset calibration should never

be required. Also, because factory 25

°C gain calibration coeffi-

cients are automatically present at power-on, an internal full-scale

calibration will only be required if the part is being operated at

temperatures significantly different from 25

°C or away from the

calibration conditions. The AD7719 offers “internal” or “sys-

tem” calibration facilities. For full calibration to occur on the

selected ADC, the calibration logic must record the modulator

output for two different input conditions. These are “zero-scale”

and “full-scale” points derived by performing a conversion on

the different input voltages provided to the input of the modula-

tor during calibration. The result of the “zero-scale” calibration

conversion is stored in the Offset Calibration Registers for the

appropriate ADC. The result of the “full-scale” calibration

conversion is stored in the Gain Calibration Registers for the

appropriate ADC. With these readings, the calibration logic can

calculate the offset and the gain slope for the input-to-output

transfer function of the converter.

During an “internal” zero-scale or full-scale calibration, the

respective “zero” input and “full-scale” input are automatically

connected to the ADC input pins internally to the device. A

“system” calibration, however, expects the system zero-scale

and system full-scale voltages to be applied to the external ADC

pins before the calibration mode is initiated. In this way external

ADC errors are taken into account and minimized as a result of

system calibration. It should also be noted that to optimize

calibration accuracy, all AD7719 ADC calibrations are auto-

matically carried out at the slowest update rate.

Internally in the AD7719, the coefficients are normalized before

being used to scale the words coming out of the digital filter. The

offset calibration coefficient is subtracted from the result prior

to the multiplication by the gain coefficient.

From an operational point of view, a calibration should be treated

like another ADC conversion. A zero-scale calibration (if required)

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