AD7719 datasheet(33/40 Pages) AD

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AD7719

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Data Output Coding

When the ADC is configured for unipolar operation, the output

coding is natural (straight) binary with a zero differential input

voltage resulting in a code of 000 . . . 000, a midscale voltage

resulting in a code of 100 . . . 000, and a full-scale input voltage

resulting in a code of 111 . . . 111. The output code for any analog

input voltage on the main ADC can be represented as follows:

Code = (AIN

× GAIN × 2N)/(1.024 × V

REF)

Where AIN is the analog input voltage, GAIN is the PGA gain,

i.e., 1 on the 2.56 V range and 128 on the 20 mV range, and

N = 16 in 16-bit mode and N = 24 in 24-bit mode of operation.

The output code for any analog input voltage on the aux ADC

can be represented as follows:

Code = (AIN

× GAIN × 2N)/V

REF

Where AIN is the analog input voltage, GAIN is one or two deter-

mined by the ARN bit in the aux ADC control register, i.e., 1 on

the VREF range and 2 on the VREF/2 range and N = 16.

When an ADC is configured for bipolar operation, the coding is

offset binary with a negative full-scale voltage resulting in a code

of 000 . . . 000, a zero differential voltage resulting in a code of

100 . . . 000, and a positive full-scale voltage resulting in a code

of 111 . . . 111. The output code from the main ADC for any

analog input voltage can be represented as follows:

Code = 2

N–1

× [(AIN × GAIN/(1.024 × VREF)) + 1]

Where AIN is the analog input voltage, GAIN in the PGA gain,

i.e., 1 on the

±2.56 V range and 128 on the ±20 mV range and

N = 16 in 16 bit mode and N = 24 in 24-bit mode of operation.

The output code from the aux ADC for any analog input volt-

age can be represented as follows:

Code = 2

N–1

× [(AIN × GAIN/VREF) + 1]

Where AIN is the analog input voltage, GAIN is one or two deter-

mined by the ARN bit in the aux ADC control register, i.e., 1 on

the

± VREF range, 2 on the ± VREF/2 range, and N = 16.

Burnout Currents

The main ADC on the AD7719 contains two 100 nA constant

current generators, one sourcing current from AVDD to AIN(+),

and one sinking current from AIN(–) to AGND. The currents

are switched to the selected analog input pair. Both currents are

either on or off, depending on the Burnout Current Enable (BO)

bit in the IOCON register. These currents can be used to verify

that an external transducer is still operational before attempting

to take measurements on that channel. Once the burnout cur-

rents are turned on, they will flow in the external transducer

circuit, and a measurement of the input voltage on the analog

input channel can be taken. If the resultant voltage measured is

full-scale the user needs to verify why this is the case. A full-scale

reading could mean that the front end sensor is open circuit, it

could also mean that the front end sensor is overloaded and is

justified in outputting full-scale or the reference may be absent

and the NOXREF bit is set, thus clamping the data to all ones.

When reading all ones from the output the user needs to check

these three cases before making a judgement. If the voltage

measured is 0 V, it may indicate that the transducer has short

circuited. For normal operation, these burnout currents are

turned off by writing a 0 to the BO bit in the IOCON register.

The current sources work over the normal absolute input volt-

age range specifications with buffers on.

Excitation Currents

The AD7719 also contains two matched, software configurable

200

µA constant current-sources. Both source current from

AVDD that is directed to either the IOUT1 or IOUT2 pins of

the device. These current sources are controlled via bits in the

IOCON register. The configuration bits enable the current

sources and they can be configured to source 200

µA individu-

ally to both pins or a combination of both currents, i.e., 400

µA

to either of the selected output pins. These current sources can

be used to excite external resistive bridge or RTD sensors.

Crystal Oscillator

The AD7719 is intended for use with a 32.768 kHz watch crys-

tal. A PLL internally locks onto a multiple of this frequency to

provide a stable 4.194304 MHz clock for the ADC. The modu-

lator sample rate is the same as the crystal oscillator frequency.

The start-up time associated with 32 kHz crystals is typically

300 ms. The OSPD bit in the mode register can be used to

prevent the oscillator from powering down when the AD7719 is

placed in power-down mode. This avoids having to wait 300 ms

after exiting power-down to start a conversion at the expense of

raising the power-down current.

Reference Input

The AD7719 has a fully-differential reference input capability

for the main channel while the auxiliary channel accepts only a

single-ended reference. On the main channel, the reference inputs

REFIN1(+) and REFIN1(–) provide a differential reference

input capability. The common-mode range for these differential

inputs is from AGND to AVDD. The reference input is unbuffered

and therefore excessive R-C source impedances will introduce

gain errors. The nominal reference voltage, VREF, (REFIN1(+)

– REFIN1(–), for specified operation is 2.5 V, but the AD7719

is functional with reference voltages from 1 V to AVDD. In appli-

cations where the excitation (voltage or current) for the transducer

on the analog input also drives the reference voltage for the part,

the effect of the low frequency noise in the excitation source

will be removed as the application is ratiometric. If the AD7719

is used in a nonratiometric application, a low noise reference

should be used. Recommended reference voltage sources for

the AD7719 include the AD780, REF43, and REF192. It should

also be noted that the reference inputs provide a high impedance,

dynamic load. Because the input impedance of each reference

input is dynamic, resistor/capacitor combinations on these inputs

can cause dc gain errors, depending on the output impedance

of the source that is driving the reference inputs. Reference

voltage sources like those recommended above (e.g., AD780), will

typically have low output impedances and are therefore tolerant

to having decoupling capacitors on the REFIN1(+) without

introducing gain errors in the system. Deriving the reference

input voltage across an external resistor, as shown in Figure 19,

will mean that the reference input sees a significant external

source impedance. External decoupling on the REFIN1(+)

and REFIN1(–) pins would not be recommended in this type

of circuit configuration.

The auxiliary channel conversion results are based on the volt-

age applied to REFIN2. This is a single-ended reference input

specified for 2.5 V operation but functional with input voltages

from 1 V to AVDD.

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