WM8903 datasheet(101/178 Pages) WOLFSON

101 / 178 page

Production Data

WM8903

PD, Rev 4.5, June 2012

101

DIGITAL MICROPHONE (DMIC) OPERATION

When GPIO1/DMIC_LR is configured as DMIC_LR Clock output, the WM8903 outputs a clock which

supports Digital Microphone operation at a multiple of the ADC sampling rate. The precise clock

frequency varies according to the MCLK frequency, the SAMPLE_RATE field and other settings. The

clock frequency is always within the range 1MHz - 3MHz, and some examples are shown in Table 66.

SAMPLE

RATE

CLK_SYS

RATIO

DMIC_LR

FREQUENCY

DMIC_LR RATIO

8kHz

12.288MHz

1536fs

1.024MHz

128fs

8kHz

12MHz

1500fs

1.200MHz

150fs

16kHz

12.288MHz

768fs

2.048MHz

128fs

16kHz

12MHz

750fs

2.400MHz

150fs

48kHz

12.288MHz

256fs

1.536MHz

32fs

48kHz

12MHz

250fs

2.400MHz

50fs

44.1kHz

11.2896MHz

256fs

2.822MHz

64fs

44.1kHz

12MHz

272fs

3.000MHz

68fs

32kHz

12MHz

375fs

2.400MHz

75fs

24kHz

12MHz

500fs

2.400MHz

100fs

12kHz

12MHz

1000fs

1.500MHz

125fs

Table 66 Digital Microphone Clock

Note that the 88.2kHz and 96kHz sample rate settings are not valid for Digital Microphone operation.

FREQUENCY LOCKED LOOP (FLL)

The integrated FLL can be used to generate CLK_SYS from a wide variety of different reference

sources and frequencies. The FLL can use either MCLK, BCLK or LRC as its reference, which may

be a high frequency (eg. 12.288MHz) or low frequency (eg. 32.768kHz) reference. The FLL is tolerant

of jitter and may be used to generate a stable CLK_SYS from a less stable input signal. The FLL

characteristics are summarised in “Electrical Characteristics”.

Note that the FLL can be used to generate a free-running clock in the absence of an external

reference source. This is described in the “Free-Running FLL Clock” section below.

The FLL is enabled using the FLL_ENA register bit. Note that, when changing FLL settings, it is

recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other

recommended the FLL be reset by setting FLL_ENA to 0.

The FLL_CLK_SRC field allows MCLK, BCLK or LRC to be selected as the input reference clock.

The field FLL_CLK_REF_DIV provides the option to divide the input reference (MCLK, BCLK or LRC)

by 1, 2, 4 or 8. This field should be set to bring the reference down to 13.5MHz or below. For best

performance, it is recommended that the highest possible frequency - within the 13.5MHz limit -

should be selected.

The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only the

default setting be used for this parameter. FLL_GAIN controls the internal loop gain and should be set

to the recommended value quoted in Table 69.

The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real

number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the

fractional portion of the number (MSB = 0.5). The fractional portion is only valid in Fractional Mode

when enabled by the field FLL_FRAC.

It is recommended that fractional Mode (FLL_FRAC = 1) is selected at all times. Power consumption

in the FLL is reduced in integer mode; however, the performance may also be reduced, with

increased noise or jitter on the output.

If low power consumption is required, then FLL settings must be chosen when N.K is an integer (ie.

FLL_K = 0). In this case, the fractional mode can be disabled by setting FLL_FRAC = 0.

WM8903 Datasheet(PDF) 101 Page - Wolfson Microelectronics plc

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