WM8903 datasheet(105/178 Pages) WOLFSON

105 / 178 page

Production Data

WM8903

PD, Rev 4.5, June 2012

105

FREE-RUNNING FLL CLOCK

The FLL can generate a clock signal even when the external reference is removed. It should be noted

that the accuracy of this clock is reduced, and a reference source should always be used where

possible. In free-running modes, the FLL is not sufficiently accurate for hi-fi audio applications. The

free-running modes are suitable for clocking other functions, including the Write Sequencer and DC

servo control. The free-running mode can be used to support the analogue input (bypass) audio

paths.

A clock reference is required for initial configuration of the FLL as described above. For free-running

operation, the FLL_HOLD bit should be set, as described in Table 69. When FLL_HOLD is set, the

FLL will continue to generate a stable output clock after the reference input is stopped or

disconnected.

Note that the FLL must be selected as the CLK_SYS source by setting CLK_SRC_SEL (see Table

61). Note that, in the absence of any reference clock, the FLL output is subject to a very wide

tolerance. See “Electrical Characteristics” for details of the FLL accuracy.

GPIO OUTPUTS FROM FLL

The WM8903 has an internal signal which indicates whether the FLL Lock has been achieved. The

FLL Lock status is an input to the Interrupt control circuit and can be used to trigger an Interrupt event

- see “Interrupts”.

The FLL Lock signal can be output directly on a GPIO pin as an external indication of FLL Lock. See

“General Purpose Input/Output (GPIO)” for details of how to configure a GPIO pin to output the FLL

Lock signal.

The FLL Clock can be output directly on a GPIO pin as a clock signal for other circuits. Note that the

FLL Clock may be output even if the FLL is not selected as the WM8903 CLK_SYS source. The

clocking configuration is illustrated in Figure 55. See “General Purpose Input/Output (GPIO)” for

details of how to configure a GPIO pin to output the FLL Clock.

EXAMPLE FLL CALCULATION

To generate 12.288 MHz output (FOUT) from a 12.000 MHz reference clock (FREF):



Set FLL_CLK_REF_DIV in order to generate FREF <=13.5MHz:

FLL_CLK_REF_DIV = 00 (divide by 1)



Set FLL_CTRL_RATE to the recommended setting:

FLL_CTRL_RATE = 000 (divide by 1)



Set FLL_GAIN to the recommended setting:

FLL_GAIN = 0000 (multiply by 1)



Set FLL_OUTDIV for the required output frequency as shown in Table 67:-

FOUT = 12.288 MHz, therefore FLL_OUTDIV = 2h (divide by 8)



Set FLL_FRATIO for the given reference frequency as shown in Table 68:

FREF = 12MHz, therefore FLL_FRATIO = 0h (divide by 1)



Calculate FVCO as given by FVCO = FOUT x FLL_OUTDIV:-

FVCO = 12.288 x 8 = 98.304MHz



Calculate N.K as given by N.K = FVCO / (FLL_FRATIO x FREF):

N.K = 98.304 / (1 x 12) = 8.192



Determine FLL_N and FLL_K from the integer and fractional portions of N.K:-

FLL_N is 8. FLL_K is 0.192



Confirm that N.K is a fractional quantity and set FLL_FRAC:

N.K is fractional. Set FLL_FRAC = 1.

Note that, if N.K is an integer, then an alternative value of FLL_FRATIO should be selected

in order to produce a fractional value of N.K.

WM8903 Datasheet(PDF) 105 Page - Wolfson Microelectronics plc

WM8903 Datasheet(HTML) 105 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL