WM8903 datasheet(104/178 Pages) WOLFSON

104 / 178 page

WM8903

Production Data

PD, Rev 4.5, June 2012

104

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

10:9

FLL_CLK_REF

_DIV [1:0]

FLL Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference) must

be divided down to <=13.5MHz.

For lower power operation, the

reference clock can be divided down

further if desired.

8:6

FLL_CTRL_RA

TE [2:0]

000

Frequency of the FLL control block

000 = FVCO / 1 (Recommended value)

001 = FVCO / 2

010 = FVCO / 3

011 = FVCO / 4

100 = FVCO / 5

101 = FVCO / 6

110 = FVCO / 7

111 = FVCO / 8

Recommended that this register is not

changed from default.

5:3

FLL_OUTDIV

[2:0]

000

FOUT clock divider

000 = 2

001 = 4

010 = 8

011 = 16

100 = 32

101 = 64

110 = 128

111 = 256

(FOUT = FVCO / FLL_OUTDIV)

2:0

FLL_FRATIO

[2:0]

000

FVCO clock divider

000 = divide by 1

001 = divide by 2

010 = divide by 4

011 = divide by 8

1XX = divide by 16

000 recommended for FREF > 1MHz

100 recommended for FREF < 64kHz

R130 (82h)

FLL Control 3

15:0

FLL_K [15:0]

0000h

Fractional multiply for FREF

(MSB = 0.5)

R131 (83h)

FLL Control 4

9:0

FLL_N [9:0]

000h

Integer multiply for FREF

(LSB = 1)

Table 69 FLL Register Map

WM8903 Datasheet(PDF) 104 Page - Wolfson Microelectronics plc

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