WM8903 datasheet(103/178 Pages) WOLFSON

103 / 178 page

Production Data

WM8903

PD, Rev 4.5, June 2012

103

Note that FREF is the input frequency, after division by FLL_CLK_REF_DIV, where applicable.

In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field.

This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if

desired, the value of this field may be calculated by multiplying K by 2

16 and treating FLL_K as an

integer value, as illustrated in the following example:

If N.K = 8.192, then K = 0.192

Multiplying K by 2

16 gives 0.192 x 65536 = 12582.912 (decimal)

Apply rounding to the nearest integer = 12583 (decimal) = 3127 (hex)

For best performance, FLL Fractional Mode should always be used. Therefore, if the calculations

yield an integer value of N.K, then it is recommended to adjust FLL_FRATIO in order to obtain a non-

integer value of N.K. Care must always be taken to ensure that the FLL operating frequency, FVCO, is

within its recommended limits of 90-100 MHz.

The register fields that control the FLL are described in Table 69. Example settings for a variety of

reference frequencies and output frequencies are shown in Table 70.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R128 (80h)

FLL Control 1

7:4

FLL_GAIN [3:0]

Gain applied to error

0000 = x 1 (Recommended value)

0001 = x 2

0010 = x 4

0011 = x 8

0100 = x 16

0101 = x 32

0110 = x 64

0111 = x 128

1000 = x 256

Recommended that this register is not

changed from default.

FLL_HOLD

FLL Hold Select

0 = Disabled

1 = Enabled

This feature enables free-running

mode in FLL when reference clock is

removed

FLL_FRAC

Fractional enable

0 = Integer Mode

1 = Fractional Mode

Fractional Mode is recommended in all

cases

FLL_ENA

FLL Enable

0 = Disabled

1 = Enabled

R129 (81h)

FLL Control 2

12:11

FLL_CLK_SRC

[1:0]

FLL Clock source

00 = MCLK

01 = BCLK

10 = LRC

11 = Reserved

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