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82575EB Datasheet(PDF) 7 Page - Intel Corporation |
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82575EB Datasheet(HTML) 7 Page - Intel Corporation |
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7 / 62 page ![]() Features of the 82575EB Gigabit Ethernet Controller — Intel® 82575EB Gigabit Ethernet Controller 317679-004 Intel® 82575EB Gigabit Ethernet Controller Revision: 2.11 Datasheet January 2011 7 2.0 Features of the 82575EB Gigabit Ethernet Controller 2.1 PCI Express Features 2.2 MAC-Specific Features Features Benefits Uses x4 PCI Express interface on MCH device. Supports x4, x2, and x1 modes. • Bus sharing not required • Low latency path to memory • Relieves congestion for IO devices connected to ICH Peak bandwidth 2 GB/s in each direction per PCI Express lane • Supports Gigabit Ethernet at full wire speed PCI Express Power Management • Compatible extensions to PCI power management and ACPI • PE_WAKE available for wakeup event High bandwidth density per pin • Less congested board routing 64-bit address support for systems using more than 4 GB of physical memory Features Benefits I/O Acceleration Technology2 (IOAT2) • Accelerated TCP I/O. Four optimized transmit and receive queues • Network packets handled without waiting or buffer overflow. IEEE 802.3x compliant flow control support with software controllable pause times and threshold values • Control over the transmissions of pause frames through software or hardware triggering • Frame loss reduced from receive overruns Caches up to 64 packet descriptors (per queue) • Efficient use of PCI Express bandwidth Separate transmit and receive queues per port • Efficient packet prioritization Programmable host memory receive buffers (256 Bytes to 16 KBytes) and cache line size (64 Bytes to 128 Bytes) • Efficient use of PCI Express bandwidth Wide, pipelined internal data path architecture • Low latency data handling • Superior DMA transfer rate performance Dual 8 KByte configurable Transmit and Receive FIFO buffers • No external FIFO memory requirements • FIFO size adjustable to application Descriptor ring management hardware for transmit and receive • Simple software programming model Optimized descriptor fetching and write-back mechanisms • Efficient system memory and use of PCI Express bandwidth Mechanism available for reducing interrupts generated by transmit and receive operations • Maximizes system performance and throughput |
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