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Introduction — Intel® 82575EB Gigabit Ethernet Controller

317679-004

Intel® 82575EB Gigabit Ethernet Controller

Revision: 2.11

Datasheet

January 2011

1.0

Introduction

The Intel® 82575EB Gigabit Ethernet Controller is a single, compact component with two fully

integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. The device uses

the PCI Express Base Specification, Rev.1.1RD.

The 82575EB provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and

10BASE-T applications (802.3z, 802.3u, and 802.3ab). Ports also contain a Serializer-Deserializer

(SERDES) to support 1000Base-SX/LX (optical fiber) and Gigabit backplane applications. In addition to

managing MAC and PHY Ethernet layer functions, the controller manages PCI Express packet traffic

across its transaction, link, and physical/logical layers. The SERDES can be used in SGMII mode to

connect to external PHY, either on-board or via the SFP connector.

The Intel 82575EB’s on-board System Management Bus (SMB) ports enable network manageability

implementations required by information technology personnel for remote control and alerting via the

LAN. With SMB, management packets can be routed to or from a management processor. Enhanced

pass-through capabilities also allow system remote control over standardized interfaces. Also included

is a new manageability interface, NC-SI that supports the DMTF preOS sideband protocol. An internal

management interface called MDIO enables the MAC (and software) to monitor and control the PHY.

Both ports support the Wake on LAN feature.

The 82575EB with PCI Express architecture is designed for high performance and low memory latency.

The device is optimized to connect to a system Memory Control Hub (MCH) using four PCI Express

lanes. Alternatively, the 82575EB can connect to an I/O Control Hub that has a PCI Express interface.

Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and

data words. Combining a parallel and pipe-lined logic architecture optimized for Gigabit Ethernet and

independent transmit and receive queues, the 82575EB efficiently handles packets with minimum

latency. The 82575EB includes advanced interrupt handling features, including MSI-X support. The

82575EB uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached

on chip. A large 48 KByte per port on-chip packet buffer maintains superior performance. In addition,

using hardware acceleration, the controller offloads tasks from the host, such as TCP/UDP/IP checksum

calculations and TCP segmentation.

The 82575EB operation can be configured using EEPROM and FLASH; it can be also be used in EEPROM-

less configurations.

The 82575EB is packaged in a 25mm X 25mm, 576-pin flip chip ball grid array (FCBGA).

1.1

Document Scope

This document contains targeted datasheet specifications for the 82575EB, including signal

descriptions, DC and AC parameters, packaging data, and pinout information.

82575EB Datasheet(PDF) 5 Page - Intel Corporation

82575EB Datasheet(HTML) 5 Page - Intel Corporation

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