FLEX10KA datasheet(55/128 Pages) ALTERA

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Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 23. Output Drive Characteristics for EPF10K250A Device

Timing Model

The continuous, high-performance FastTrack Interconnect routing

resources ensure predictable performance and accurate simulation and

timing analysis. This predictable performance contrasts with that of

FPGAs, which use a segmented connection scheme and therefore have

unpredictable performance.

Device performance can be estimated by following the signal path from a

source, through the interconnect, to the destination. For example, the

registered performance between two LEs on the same row can be

calculated by adding the following parameters:

■

LE register clock-to-output delay (tCO)

■

Interconnect delay (tSAMEROW)

■

LE look-up table delay (tLUT)

■

LE register setup time (tSU)

The routing delay depends on the placement of the source and destination

LEs. A more complex registered path may involve multiple combinatorial

LEs between the source and destination LEs.

VCCINT = 3.3 V

VCCIO = 3.3 V

Room Temperature

VCCINT = 3.3 V

VCCIO = 2.5 V

Room Temperature

VO Output Voltage (V)

1234

VO Output Voltage (V)

1234

IOL

IOH

IOL

IOH

Typical IO

Output

Current (mA)

Typical IO

Output

Current (mA)

FLEX10KA Datasheet(PDF) 55 Page - Altera Corporation

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